Mismatch between Deep Learning HDL Estimator and Vivado Resource Utilization

Hi,

I'm deploying a Deep Learning HDL processor on the ZCU102 Evaluation Kit. I am using the following processor configuration:

hPC.TargetPlatform   = 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit';
hPC.TargetFrequency  = 200;   % MHz
hPC.SynthesisTool    = 'Xilinx Vivado';
setModuleProperty(hPC,'conv','InputMemorySize', [255 255 3]);
setModuleProperty(hPC,'conv','InputMemorySize', [123 123 16]);
setModuleProperty(hPC,'conv','FeatureSizeLimit', 1024);
setModuleProperty(hPC,'conv','LRNBlockGeneration','off');
setModuleProperty(hPC,'conv','SegmentationBlockGeneration','off');
setModuleProperty(hPC,'conv','WeightBlockGeneration','false');
setModuleProperty(hPC,'fc','ModuleGeneration','off');
setModuleProperty(hPC,'custom','Resize2D','on'); 
setModuleProperty(hPC,'custom','Addition','off');  
setModuleProperty(hPC,'custom','Identity','off');  
setModuleProperty(hPC,'custom','Multiplication','off'); 

When I run the resource estimation in MATLAB, I obtain the following result:

The issue is that when I generate the complete design (reference + DL processor) bitstream in Vivado, I get the following results:

Why does the final bitstream use 90% of the FPGA CLB resources?

Thanks,

Juan

Answer 1

[Yashwanth]

Hi Juan,

I believe the final bitstream uses ~90% CLB resources because Vivado adds timing-closure, interconnect, control, and clocking logic on top of the estimated Deep Learning Processor resources, and this overhead grows rapidly at high clock frequencies (200 MHz).

[Juan Martin de las mulas]

Hi Yashwanth,

Thanks! However, Matlab’s resource estimation also shows an estimation of this additional logic on top (I assume the “total estimation” should be more or less the same). The estimation is also performed considering the frequency.

Thank you,

Juan