FPGA in the loop Workflow

I need more help understanding the FPGA in the loop verification workflow. I have PMSM controller in Simulink that was converted to HDL using Workflow Advisor. In the simulink model, I have Simscape blocks that model the motor, current sensors, and encoder. I convert these values to a format that represents what I expect to receive from the hardware ADCs and write the result to an AXI4 Random Access Memory block. The controller block has an simplified AXI4 master interface that can then read these values. For the purposes of the FPGA-in-the-loop verification I want to create an AXI4 slave device that will respond with the exact same ADC values for each time step that the HDL DUT device attempts to read the sensor data. I also want to log this data so it can be compared with the Simulink simulation results. Each time step the DUT also controls the output of 6 GPIO pins that go to a 3 phase inverter. I want to record their outputs as well. Does the HDL verifier provide some automated way of doing this? If so, is there some clear documentation on how this works and maybe some examples? I'm using an Altera Cyclone V on a custom board. Thank you for any assistance.