How to configure host interface and setup scripts for FPGA I/O?

Dear all,

I am making a design for an RFSoC device using SoC Blockset add-on.

I have deployed the design, now I want to save data from the FPGA using host interface script (https://www.mathworks.com/help/hdlcoder/ug/generate-host-interface-script-to-probe-and-rapidly-prototype-hdl-ip-core.html) generated during the build by SoC Builder tool.

In this script I removed register interfaces, as my design has none of them yet (I also wonder why they were generated), and left only one interface (AXI4-Stream), to record data from the last IP in the design (which further streams data to the PS, but this is not the scope of the question). The host interface script and the setup functions are attached, I did not alter the "addAXI4StreamInterface" and "DUTPort" setup, they are left in the form in which they were generated.

There is no logic in the script yet, I just tried to run it to see whether the connection is established successfully and whether the interface setup works fine.

However, when I run the host interface script, I get the following error:

>> gs_Top_interface

Error using fpgaio.interface.InterfaceBase/mapPort

Unable to map port(s) "data_PS_Interface_512StreamRead0".

Error in fpgaio.FPGA/mapPort

Error in gs_Top_setup (line 18)

mapPort(hFPGA, h_data_PS_Interface_512StreamRead0);

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Error in

gs_Top_interface (line 3)

gs_Top_setup(hFPGA);

^^^^^^^^^^^^^^^^^^^^^^^^

Caused by:

Error using fpgaio.interface.AXI4Stream/validatePort

Port width "128" for port "data_PS_Interface_512StreamRead0" is too large for interface "PS_Interface_512StreamRead0". The port width must be less than or equal to

the interface's "WriteDataWidth or ReadDataWidth" value of "32". Change the data type on the port to have smaller width.

In the top model and in the FPGA model the signal that I want to record using this script looks like this:

I might be wrong, but it seems like the "addAXI4StreamInterface" and "DUTPort" configuration in the setup script is incorrect.

Do you have any ideas on how to resolve this? Thank you!

[Sergei]

P.S.: to explain why "ReadFrameLength" is automatically set to be 131072 and "ReadDataWidth" is set to be 32:

One buffer consists of 131072 32bit samples, which are written to the PS RAM in batches of four samples concatenated to a 128bit sample, which are packed into a package of 32 samples, with the resulting bitwidth of 4096bit. This is done due to that 4096 is the max bitwidth the AXI4-Stream to Software block supports by default, and the samples are concatenated due to that for some reason simulation shows this makes the transfers faster. But the buffer is read by the processor normally, as 131072 32bit samples.

So, 128 32bit samples -> concatenation -> 32 128bit samples -> AXI4-Stream to SW -> stream read -> 131072 32bit samples.

That is why in my understanding the values are generated in this way in the setup script.

Answer 1

[Abhipsa]

Hii @Sergei, The issue is caused by a data width mismatch between your DUT AXI4-Stream port and the host interface definition. The DUT stream signal is 128 bits wide, while the host interface was configured for 32-bit stream data. For AXI4-Stream, the TDATA width of the DUT port must be compatible with the interface ReadDataWidth setting.

You can resolve this in one of two ways:

Option 1: Match the host interface to the DUT width

Configure the host interface with ReadDataWidth = 128 and, if your logical samples are uint32, use a Sample Packing Factor of 4 to represent 4×32-bit elements per 128-bit beat.

Relevant documentation:

• addAXI4StreamInterface (see ReadDataWidth and SamplePackingFactor): https://www.mathworks.com/help/releases/R2025a/hdlcoder/ref/addaxi4streaminterface.html
• hdlcoder.DUTPort (use to describe vector/packed data): https://www.mathworks.com/help/releases/R2025a/hdlcoder/ref/hdlcoder.dutport.html
• mapPort (to associate the DUT signal with the interface): https://www.mathworks.com/help/releases/R2025a/hdlcoder/ref/mapport.html

If the stream represents multiple samples per beat, the SoC Blockset documentation explains how packed frame transfer works: https://www.mathworks.com/help/releases/R2025a/soc/ref/axi4streamtosoftware.html

Option 2: Keep the host interface at 32 bits (no packing on host)

Insert a stream width converter in your FPGA platform design (e.g., between DUT stream output and DMA input) to reduce the stream width to 32 bits. This shifts unpacking logic into hardware instead of software.

I hope this helps you

[Sergei]

@Abhipsa, thank you for you answer!

I have set "SamplePackingFactor" to 4 and "ReadDataWidth" to 128. Now I get another error:

>> gs_Top_interface
Error using matlabshared.libiio.base/cstatusid
Data size mismatch.

Error in matlabshared.libiio.base/setupImpl

Error in matlabshared.libiio.axistream.read/setupImpl

Error in fpgaio.driver.AXIStreamIIORead/setup

Error in fpgaio.interface.AXI4Stream/setup

Error in fpgaio.interface.AXI4Stream

Error in fpgaio.FPGA/addAXI4StreamInterface

Error in gs_Top_setup (line 3)
    addAXI4StreamInterface(hFPGA, ...
    ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Error in gs_Top_interface (line 3)
gs_Top_setup(hFPGA);
^^^^^^^^^^^^^^^^^^^

I thought this might be due to that "ReadFrameLength".

I thought this might be due to that "ReadFrameLength" must then also be adjusted to 131072/4, but this did not help, the same error arises. Also from the documentation on "addAXI4StreamInterface" it is clear that the "ReadFrameLength" should stay the same.

Do you have any thoughts on what might the problem be?

Thank you!