Expose a RAM port to top for HDL Coder core?

For a processing algorithm we are developing targeting a Xilinx IP core, we have a couple ports that carry "normal" register settings, and then we have a RAM that is to store a set of filter coefficients (36x8k, I could trim to 32x8k to make it easier) that the software should load prior to startup. Right now I hand-build a signal that carries the data, address, and a write enable from a top level port into the RAM write port. It will work but it's clunky. Given that an AXI-Lite slave is already a memory-mapped interface, is there a more elegant solution where I can just define the start address for the RAM and have it create the right signals to include it in my address map? Otherwise I might have it skip the AXI wrapping and just make it a custom port and hand-code some HDL to run it.

[Martin Ryba]

Reviewing some docs further, I guess I could give the RAM its own AXI4 Slave Interface by creating a bus object (or multiple ports) with the right signals. It would add more lines to the block design but I guess Vivado would be OK with that.

On the other hand, maybe not. Saw other documentation saying you can have either an AXI4-Lite Slave or a AXI4 Slave but not both. You can have multiple stream masters or slaves, but not multiple register interfaces.

[Martin Ryba]

I also tried converting it to a Dual Rate Dual Port RAM to allow the coefficient writing to be on a different clock domain (which will tend to be true for AXI4-Lite registers). Won't work. Block throws an error when you write to whatever address the (idle) reading section happens to be pointing to. Unavoidable crash.

Tried converting the entire section to a 1-D table lookup with the input table being the port. After mucking around to make it no longer complex data, hit the error that the AXI4 limits you to 4096 length vectors (mine is 8192) :( I guess I can make two 4k vectors and concatenate them inside, but that's stupid and since the lengths are all parameterized it breaks that.

Answer 1

[Martin Ryba]

After some help from Faye in tech support, got past the Dual Rate Dual Port RAM issue (need to disable the assertion), and decided that for now the best option is to make the RAM signals on the B side route to top level ports that then are just set to External Port in the HDL Coder interface mapping. Those signals can then be connected to a AXI BRAM Controller IP block which controls a standard RAM interface via an AXI4-Lite interface. It will have its own base address, but's that's fine I can just put it next to the one for the "normal" ports.