I understand that you are experiencing issues when transitioning from an energy-buffered load (battery) to a passive one (resistive). I will address your questions one by one:
Q1. Why does the system behave well with a battery load, but not with a resistive load?
Ans: The main reason for this issue is the lack of DC bus voltage regulation with resistive load. Battery load and resistive load differ in the implications as follows:
- Battery Load: It acts as a voltage source on the DC side. It stabilizes the DC link, effectively regulating the DC bus voltage for the controller. The VSC simply manages current flow to maintain voltage balance and control power.
- Resistive Load: Whereas Resistive load acts as a current sink that pulls power continuously from the DC bus. In this configuration, if your control loop is not regulating the DC link voltage (e.g., via a power balance loop), the DC bus voltage can drop or oscillate, making the control unstable.
Solution: To solve this issue, you can try implementing a DC bus voltage control loop. Use an outer DC voltage control loop that adjusts the d-axis current reference ("Id_ref") for the inner current loop. Also, this loop ensures power delivered to the DC bus matches what is drawn by the resistive load.
Q2. What could cause a non-zero negative-sequence Vd (~1.5 V) under balanced conditions?
Ans: I think under ideally balanced conditions, the negative-sequence component should be negligible. A few potential causes for the above behaviour could be:
a. Imperfect SOGI Tuning
- If the "SOGI-QSG" (Quadrature Signal Generator) or the PLL bandwidth is too wide or too narrow, it can leak harmonics or unbalance into the sequence extraction.
- You can read more about "SOGI" here: https://www.mathworks.com/matlabcentral/fileexchange/146626-sogi-and-fll-simulations
b. Numerical or Implementation Artifacts
- Sometimes finite sampling, discretization delay, or unfiltered noise or filter initialization artifcats (in Simulink) could result in an apparent negative-sequence offset.
c. Filter Interaction
- The "LCL" filter resonance or poorly damped response can inject asymmetries during transient conditions.
- Especially if RC damping isn't properly tuned, the resonance peak may cause small phase and magnitude distortion in one or more phases, resulting in sequence imbalance.
- You can read more about "LCL" filter here: https://www.mathworks.com/matlabcentral/fileexchange/53377-lcl-filter-design-inlcuding-the-current-control-tuning
Q3. How should I tune the SOGI filter or control loops to improve stability and accuracy during resistive loading?
Ans: You can try the following for tuning SOGI filter to improve stability and accuracy during resistive loading.
- SOGI Gain (K): You can use ~1.414 for good balance between speed and filtering.
- PLL Bandwidth: Try setting BW to 10–20 Hz for stable tracking and harmonic rejection.
You may also want to keep the following points in mind to improve control performance:
- Ensure adequate DC bus capacitance for energy buffering.
- Use a small simulation step size (1e-6 to 1e-5 s) for accuracy.
- Monitor PLL and controller response during transitions.
These adjustments improve control stability and accuracy, especially under passive (resistive) loading conditions.
Hope it helps!
