Issue with Implementing System Clock Constraint in FPGA in the Loop (FIL) Toolbox

Hi all,

I'm working with the FPGA-in-the-Loop (FIL) toolbox and trying to perform FIL on the Alinx AXU2CGB board. During the validation process in custom board creation, I encountered a DRC error at the implementation stage due to an invalid pin for the system clock.

To resolve this, I opened the project in Vivado and added the following constraint to the XDC file:

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sys_Clk]

This allowed the bitstream to generate successfully in Vivado 2019.1. However, I would like to know how to implement the same constraint directly in the FIL wizard steps.

Can anyone guide me on how to add this clock constraint in the FIL toolbox?

Thanks in advance for your help!

Answer 1

[YP]

you can save the custom constraints as an .xdc file, and add the xdc file as the source files in FIL Wizard.

click 'Add', choose 'Constraint files (*.xdc)' in the dropdown list, and select your own xdc file.

[Danish Anwar]

Hi,

Thank you for your response—it helped resolve the issue, and I was able to generate the bitstream successfully.

However, when I load the image onto the FPGA and run the simulation, I encounter the following error (see attached figure):

My board uses a 25 MHz external clock, which I have configured as the system clock. I also set the clock frequency to 25 MHz in the "Advanced Options" section of the FIL Wizard.

Also I'm using MATLAB 2019a and Vivado 2019.1.

Could you please help me understand what might be causing this issue?

Best regards,

[YP]

The 25MHz in the filWizard is the DUT running frequency. You don't need to make it same as board external clock.

Your JTAG interface definition could be wrong. Please share how you create the custom board, and board manual.

[Danish Anwar]

Thank you for your response. Could you please let me know how to verify the JTAG settings?

Below are the current board settings and the default JTAG configuration I'm using:

I'm using AXU2CGB board by ALINX link to the board manual is show below: https://alinx.com/public/upload/file/AXU2CGAB_User_Manual.pdf

I'm also sharing the XML file of the board verfication

Answer 2

[YP]

Make the following changes, and try again.

• Sum of IR lengths AFTER: 4
• User1 Instruction: 100100000010
• User2 Instruction: 100100000011
• User3 Instruction: 100100100010
• User4 Instruction: 100100100011
• JTAG Clock Frequency (MHz): 30

[Danish Anwar]

Are these parameters specific to the board?

[YP]

it is device specific.

check https://www.mathworks.com/help/hdlverifier/ug/fpga-board-editor-reference.html

about IR length for Zynq, and how to get user instruction, jtag clock from bsd files.

The bsd file can be downloaded from

https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models.html

[Danish Anwar]

I have tested with these value but unfortunately still getting same error. One difference I find in your instruction and the link you sent is that the mention to set

"If you are using a Zynq® device, and it is the only item in the device chain, enter 4 in Sum of IR length before and 0 in Sum of IR length after."

But in your instruction you said " Sum of IR lengths AFTER: 4" should I try with

• Sum of IR lengths before: 4
• Sum of IR lengths AFTER: 0

Thanks

[YP]

Since your JTAG position is 1, the sum of IR lengths before/after should be 0/4. For Zynq-7000 devices, since JTAG position is 2, the sum of IR lengths before/after is 4/0. We will update the document to be more accurate.

There are some issues to consider:

• Make sure you downloaded the bitstream before running the simulation. We've seen customers forget to do so.
• Your specified part is xczu2cg-sfvc784-1-e. However, it is listed as xczu2cg-1sfvc784e in the manual. What is the actual part you see in the Vivado hardware manager?
• To solve the placement error, try adding a BUFG between sysclk and clock_wiz as follows, and do not set the CLOCK_DEDICATED_ROUTE constraint. Generate the new bitfile, and re-retry. Notice the new bitfile will be located under project folder -> *.runs -> impl_1

-- Add this signal after the BitZero signal declaration:

SIGNAL sysclk_bufg : std_logic;

-- Add this component declaration after the other component declarations:

COMPONENT BUFG

PORT (

I : in STD_LOGIC;

O : out STD_LOGIC

);

END COMPONENT;

-- Add this instance in the architecture body before the clock wizard:

sysclk_buf : BUFG

PORT MAP (

I => sysclk,

O => sysclk_bufg

);

-- Modify the clock wizard port map to use sysclk_bufg:

u_clk_wiz_0: clk_wiz_0

PORT MAP(

locked => locked,

clk_in1 => sysclk_bufg, -- Changed from sysclk to sysclk_bufg

clk_out1 => dutClk,

reset => dcm_reset

);

[Danish Anwar]

Hi,

Thanks for your response.

• Yes I make sure that bit file loaded by opening block generated for FIL and Loading the bit and it shows bit file loaded sucessfully.
• I used same part no in Vivado and it works fine. The part no. showing on the screen is generated by FIL wizard.
• How can I add buffer or modify RTL as everything is auto generated. Can we manually edit the Vivado project and its works with FIL?

Thanks

[YP]

Yes, you need to do it manually.

1. Run FilWizard, don't include your own xdc file.
2. Vivado should fail due to placement error.
3. Open Vivado project and modify the top file as above.
4. Generate bit and download