How do I configure the RF DataConvertor sample clock distribution when using an External PLL

I'm using a ZCU208 board fitted with a 3rd generation RFSoC device. These devices are capable of distrubuting an externally generated sample clock between the RF tiles. Can you advise me where this configuration can be applied in the Data Converor block? I've only been able to find the External PLL selection but not the distribution configuration.

Thanks

Mike

[Tom Richter]

Hi Mike,

You might talk about Multi-Tile Synchronization. We have an example here. If this is not what you are looking for, please provide more information and links to AMD user guides where this is descriped.

Thanks,

Tom

[Michael]

Hi Tom,

I'm not specifically looking at MultiTile Synchronisation in this case but rather at the RFSoc Gen3/DFE On chip Clock Distribution described in PG269 -https://docs.amd.com/r/en-US/pg269-rf-data-converter/Sample-Rate-Clock-Forwarding-Gen-3/DFE

It is possible to define a RF tile as the clock source and the forward this clock to other tiles in the group.

" The forwarded clock can be

1. External sampling clock
2. External reference clock used with internal PLLs
3. Sampling clock generated by on-chip PLL "

In the case of the ZCU208 board an external sampling rate clock feeds into DAC2 and ADC1 but an external reference clock for the on tile PLLs feeds into DAC0 and ADC2.

Thanks

Mike