How to use JTAG AXI manager to access BRAM in VCU118 FPGA board?

I have been trying to use JTAG AXI manager example for my VCU118 board to write itno FPGA memories (BRAM and DDR). I have HDL verifier and FPGA board support package for xilinx. I created an empty project in vivado and then using following two lines

hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath', ...
                 'C:\Xilinx\Vivado\2023.2\bin\vivado.bat');
project_path = 'C:\project\basic_demo\basic_demo.xpr';
setupAXIManagerForVivado project_path

But I get an error "Unrecognized function or variable 'setupAXIManagerForVivado'.".

Let me know what am I missing ?

Hardware side everything is working at my end , as I have been able to program FPGA using JTAG cable directlly using VIVADO.

Answer 1

[Saurabh]

Hi Risi,

It appears that you are running into a problem while attempting to write to FPGA memories with the JTAG AXI manager for the VCU118 board. I'm not sure why you are experiencing this, looking at the error. I can recommend a few troubleshooting actions:

• Ensure that the "HDL Verifier and FPGA Board Support Package" are correctly installed. Sometimes, components may not install properly, leading to missing functions. Verify that you have the correct version of these toolboxes compatible with your MATLAB release.
• Search for the “setupAximanagerForVivado” function in installation directory to confirm its existence. You can use “which” command in MATLAB to see if the function can be located or “exist” command to check its existence:

 which setupAXIManagerForVivado
 % or
 exist setupAXIManagerForVivado

• Currently there is no exact demo showcasing MATLAB Ethernet AXI Manager to transmit data between a Xilinx VCU118 evaluation board and MATLAB. But they can refer to the example "https://www.mathworks.com/help/hdlverifier/xilinxfpgaboards/ug/access-fpga-mem-using-ethernet-aximaster.html".
• This example demonstrates how to integrate Ethernet-based AXI manager into a Xilinx Vivado project and how to write and read from the DDR memory and the BRAM using MATLAB. It has certain requirements, check if you are missing on any of them.
• VCU118 has SGMII Ethernet interface. You can refer to this doc to understand how to set up SGMII interface in Vivado design:
• "https://www.mathworks.com/help/hdlverifier/ug/ethernet-axi-manager.html"

I hope this was helpful.

[KH]

Hi Saurabh,

Most FPGAs' PLEthernet Networks are RGMII. However, the Ethernet Protocol Stack provided by Matlab only supports GMII or MII. Besides, the Xilinx IP core GMII to RGMII only supports some devices. Will Matlab provide an RGMII Ethernet Protocol Stack later?

Answer 2

[Heman P]

Hi Risi,

Good to hear that you are trying to use JTAG AXI manager example for VCU118 board.

setupAXIManagerForVivado is a part of "HDL Verifier Support Package for AMD FPGA and SoC Devices" support package of HDL Verifier product.

Can you check the "Add-Ons" section on your installed MATLAB and confirm the above mentioned SPKG name in the "Add-Ons -> Manage Add-Ons"?

Thanks,

Heman, P