How to turn off epwm using software force logic in c2000 f28388d?

Hi,

I am using an F28388D to control a 3-phase full bridge inverter. I am utilizing a code with a state diagram for this purpose. I have a requirement to completely turn off the third leg of the inverter at one point for a few seconds based on inputs from Stateflow. I tried using the software force logic, but I am unable to turn off the switches. The attached diagram shows the settings I have tried for this. I provided an input of 1 to the SW input port whenever I needed to turn off the leg, but it's not working, and I am unable to find any resources on how to implement this.

Is there anyone who can help with this?

Thanks in advance.

Regards,

Kripa

Answer 1

[Shivam Gothi]

Hello,

The parameters you configured appear to be correct. However, since I don't have access to the hardware, I am unable to determine why the PWM module is behaving unpredictably. I can suggest an alternative solution to address this issue.

To achieve the desired outcome, consider using the "TZFRC" (force a trip event) and "TZCLR" (clear trip event) registers of the F28388D microcontroller. By setting the bit EPwm1Regs.TZFRC.bit.OST to logic "1", you can trigger a one-shot event on the PWM1 module, which will disable the PWM for both the top and bottom switches (EPWM1a and EPWM1b). Similarly, setting the bit EPwm1Regs.TZCLR.bit.OST to "1" will clear the trip flag, re-enabling the PWM.

The same approach applies to the PWM2, PWM3, and PWM4 modules. For example, writing "1" to the bit EPwm2Regs.TZFRC.bit.OST will trigger a one-shot event on the PWM2 module, disabling the pulses for EPWM2a and EPWM2b.

In Simulink, you can manually write to these registers using the "Register ReadWrite" block. You can find more information on this in the MATLAB documentation linked here: https://www.mathworks.com/help/ti-c2000/ref/epwmtype14.html

In this way, you can avoid configuring any continuous software forcing logic.

Suggested Approach:

Create the following model in Simulink.

The detailed explanation for “PWM1 control logic block” is given below. Follow the same for other two “control logic block” also.

(NOTE: here, two “Register ReadWrite” blocks are used. One of it is named as “write TZFRC register” and other is named as “write TZCLR register”)

• Open the “block parameters” for “write TZFRC register” block, as shown below.

• Fill all the “unspecified” fields appropriately to get the register bit : “EPwm1Regs.TZFRC.bit.OST”. (NOTE: If the parameters on the block are 'Unspecified', configure the hardware setup using 'c2000setup' command.)
• Now open the “block parameters” for “write TZCLR register” block.
• Again, fill all the “unspecified” fields appropriately to get the register bit : “EPwm1Regs.TZCLR.bit.OST”.
• Working logic:
• When the above system receives the logic “1” from the stateflow algorithm, “Write TZFRC register” block writes “1” to the “EPwm1Regs.TZFRC.bit.OST” register bit fields. This forces a one shot event on PWM 1 module and stop the pulses .
• When the above system receives the logic “0” from the stateflow algorithm, “Write TZCLR register” block writes “1” to the “EPwm1Regs.TZCLR.bit.OST” register bit fields. This clears the trip flag and enables the PWM pulses.

I hope this is as per your expectation!

[Shivam Gothi]

Hello,

I tried the approach stated by you on hardware. I created "SFA" input port on ePWM block as mentioned by you and passed the inputs through a "constant" block as shown in below figure.

I monitored the PWM on CRO. When I made "constant" value to 1, the pulses which disabled and both the PWM outputs were cleared to "0". When I changed the "constant" value to 0, the software forcing was disabled and the PWM pulses were back again.

Please cheak the output of your stateflow algorithm. May be the stateflow algorithm might be inputting some incorrect value to "SFA" port of PWM block.

Or, try to manually pass the logic "0" and "1" by using "constant" block as shown in the above figure.

Can you please share your simulink file if possible?

[Hari]

Hello,

Thank you very much for your response.

After rigorous testing we were able to come to the following conclusions, please do correct us if we are wrong:

• The Continous Software Force (CSF) port seems to be overriden by the deadband submodule (if it is turned on), i.e, in our case both EPWMxA and EPWMxB have deadband engaged under "Active high complimenatry" mode. When we try to enagage both SFA and SFB under these conditions, only the switch chosen under Signal source for rising and falling edge (RED/FED) as shown below is pulled low while the other is puled high since the deadband polarity is set to "Acive high complimentary".

• We have a mandatory requirement for the deadband module and thus cannot run the model without it.
• We also tried using the "TZFRC" (force a trip event) and "TZCLR" (clear trip event) registers as you had mentioned and we built the model as you had suggested. Both PWM signals were successfully pulled low by the trip event, but for some reason the trip event was not clearing and the signals remained low. We still haven't figured out what we are doing wrong here.
• We were finally able to achieve our objective by using the Read/Write register blocks to manually control the AQCSFRC (Action Qualifier Continuous Software Force) register. Although as we had mentioned before, this would still not work if we do not bypass or turn off the deadband. Therefore we also added a provision to turn off the deadband for that particular EPWM block alone using another Read/Write register block as shown below:

The above configuration is able to achieve our requirement of turning off both swithches of the EPWM3 module (in this case) and re-enabling PWM as and when required.

[Ibrahim]

Hello Hari,

Were you able to figure out why the TZCLR.OST register was not setting? I am having the same issue.

Can anyone support with this, please?

Answer 2

[mosfetMax]

Hello together,

forcing a trip event by writing to TZFRC register and reseting it with TZCLR as described by @Shivam Gothi is sufficient, if TZCTL register is initialized.

For turning both ePWMs off (low logic level) in case of a trip event, TZCTL must be set to "2" (= 1,0 binary). For more information visit the technical reference manual ( https://www.ti.com/lit/ug/spruiw9c/spruiw9c.pdf?ts=1772722747833 ), especially chapter 20.9.2 at page 2272.