Xilinx RFSoC Device - HDL Workflow Advisor

I am using Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit to try MATLAB example (Pulse-Doppler Radar Using Xilinx RFSoC Device). I have installed 2022.1 Xilinx Vivado. When I used Workflow Advisor, I got error at 1.2 step (Set target reference design). I am getting below error message. I can not change the reference design tool version to "2022.1". I have also attached the screenshot of Workflow Advisor.

Failed Current reference design "Real ADC/DAC Interface with PL-DDR4" is not compatible with the version "2022.1" of "Xilinx Vivado" tool on system path. This reference design is compatible with tool version "2020.2". Please change your tool version, or use a different reference design. If you want to attempt to continue using this reference design, check the "Ignore tool version mismatch" option

Answer 1

[R]

Hi Sudantha,

The error appears to be a result of an incompatibility issue between the MATLAB Release version and the Xilinx Vivado Design Suite. Each release HDL Workflow Advisor is tested with specific versions of EDA tools. To address this, I would recommend consulting the following MATLAB Central resource to identify the versions of Vivado that are compatible with your release of HDL Coder:

Which versions of Xilinx Vivado are supported with which release of HDL Coder? - MATLAB Answers - MATLAB Central (mathworks.com)

One potential workaround is to select the "Ignore tool version mismatch" option during your workflow. Alternatively, aligning MATLAB with Vivado version 2020.2 could also bypass the compatibility issue as the HDL Coder RFSoC Hardware Support Package currently supports Vivado 2020.2. However, this approach will lead to further complications.

In this specific example, the model 'soc_range_doppler_proc' utilizes the ert.tlc system target file for the processing system (PS) part of the SoC, while 'soc_range_doppler_fpga' employs the grt.tlc for the programmable logic (PL) part. The HDL Workflow Advisor expects consistent system target file parameters across all models within the model reference hierarchy, but the unique structure of the example model does not permit this:

Given the integrated nature of the software and hardware components in the given example, the SoC Builder tool is more suitable than the HDL Workflow Advisor. SoC Builder is designed to provide a comprehensive end-to-end workflow, facilitating everything from model configuration to hardware deployment, including essential steps such as memory mapping and hardware/software interface validation. Additionally, it offers the flexibility to select build types tailored to your development requirements:

Therefore, my recommendation is to proceed with the SoC Builder tool to synthesize and deploy this design. This approach should streamline the development process and help you avoid the complexities associated with the HDL Workflow Advisor in the current context.

[Sudantha Perera]

Thank you for the answer. That was very helpful. I used SoC Builder and I coud finished the process with no error. I still can not convert the simulink model to Verilog or SystemVerilog code.

Again I am still using the example from MATLAB to generate Verilog code:openExample('xilinxsoc/RangeDopplerRADARUsingXilinxRFSoCDeviceExample')

Looks like some of the smulink bloocks and functions can not be used to generate code.

I have attached the error report. If you do not like to open the attachement. I have inclued the error discription below. 38th one is a warning. Again I appriciate any help with this.

1. Block 'soc_range_doppler_proc/Asynchronous Task Specification' is not supported for HDL code generation. To continue with code generation, comment out this block.

2. Block 'soc_range_doppler_proc/Asynchronous Task Specification1' is not supported for HDL code generation. To continue with code generation, comment out this block.

3. Trigger type 'function-call' is not supported for HDL code generation.

4. Function call port types are not supported.

5. The output port of block 'soc_range_doppler_proc/DMAReadFcn' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

6. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

7. Block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Doppler Processing/FFT' is not supported for HDL code generation. To continue with code generation, comment out this block.

8. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Doppler Processing/In1' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

9. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Doppler Processing/Abs' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

10. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Doppler Processing/FFT' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

11. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Doppler Processing/MATLAB Function' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

12. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Doppler Processing/Selector1' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

13. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Send to Host/UDP Write/Variant/CODEGEN/For Loop/In1' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

14. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Send to Host/UDP Write/Variant/CODEGEN/For Loop/For Iterator' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

15. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Send to Host/UDP Write/Variant/CODEGEN/For Loop/Selector' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

16. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Send to Host/UDP Write/Variant/CODEGEN/Data' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

17. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Send to Host/UDP Write/Variant/Data ' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

18. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Send to Host/UDP Write/Data' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

19. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Send to Host/u' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

20. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Unpack Data/Unpack Complex/In1' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

21. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Unpack Data/Unpack Complex/Data Type Conversion' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

22. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Unpack Data/Unpack Complex/Extract Bits' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

23. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Unpack Data/Unpack Complex/Extract Bits1' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

24. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Unpack Data/Unpack Complex/Real-Imag to Complex' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

25. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Unpack Data/u' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

26. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Unpack Data/Data Type Conversion' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

27. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Unpack Data/Data Type Conversion2' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

28. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Unpack Data/Reshape' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

29. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Unpack Data/Transpose' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

30. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Unpack Data/Unpack Complex' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

31. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Unpack Data/Unpack uint32 samples' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

32. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/cpiData' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

33. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Doppler Processing' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

34. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Process CPI/Unpack Data' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

35. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Stream Read/Variant/CODEGEN/AXI4-Stream Read' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

36. The output port of block 'soc_range_doppler_proc/DMAReadFcn/Stream Read/Variant/CODEGEN/AXI4-Stream Read' has a non-zero initial time offset of -2, which is unsupported for HDL code generation.

37. Data-type 'SoCData' is unsupported for HDL code generation. If Xilinx System Generator Subsystem is used, make sure it is not the top level subsystem for code generation.

38. HDL code from identical atomic subsystems can only be shared when the optimization configuration parameter 'Default parameter behavior' is set to 'Inlined'.

[R]

The example you are working with is designed to be modeled and partitioned for implementation on a System-on-Chip (SoC) platform. The system is divided into two main parts:

1. FPGA Model: This is where the range processing is performed. The model components suitable for FPGA are intended to be synthesized into HDL code.
2. Processor Model: This part handles the Doppler processing and is intended to be compiled into C code or a related language for execution on the processor.

The 'soc_range_doppler_proc' subsystem within your model is configured for the processor side of the SoC and is not meant for HDL code generation. This is why when you attempt to generate HDL code for the entire top model, including 'soc_range_doppler_proc', the process fails. The HDL code generation errors you are seeing are indicating that 'soc_range_doppler_proc' is not suitable for HDL synthesis.

On the other hand, the 'soc_range_doppler_fpga' subsystem is designed for the FPGA and you did not encounter issues when generating HDL code for it.

The SoC Builder tool is specifically designed to manage this partitioning process. It intelligently determines which parts of your model should be targeted for HDL code generation (for the FPGA) and which should be targeted for C code generation (for the processor).

Verilog code generation is typically not feasible for models designed for processor execution—this is a characteristic of an SoC implementation. To successfully build and deploy your radar system, please use the SoC Builder tool to guide you through the correct code generation process for each part of the model.

[Sudantha Perera]

Thank you!