Is the counter here working properly?

I am trying to simulate a system in Simulink as shown below. It's kindof like a sigma-delta modulator. The two switches act like comparators - when the error exceeds the upper limit, +d becomes 1, otherwise it remains 0; when the error exceeds the lower limit, -d becomes 1, otherwise it remains 0. Both counters are set to count up, when there's rising edge from +d/-d.

Now the system is not working as I expected, and I noticed some weired behaviour of the counter at the top: +d only has one rising edge but the counter starts to count even before the rising edge. Is the counter working properly, or I'm doing something wrong? I've also attached the simulink model if it helps.

[madhan ravi]

Illustrate the result with the truth table with the test cases for the conditions you specified. By the way, switches are not necessary here direct comparison can be made using compare to constant block.

[Dongxu Guo]

Hi @madhan ravi, I've converted +d and cnt_up from time series to time table and attached 2 snapshots here. cnt_up, which is the current value of the counter, starts to increase when the signal at Inc port remains 0. When there's an actual rising edge (at row 98) the counter value jumps from 252 to 3. By the way, thanks for your advice about using compare to constant, it really helps.

[madhan ravi]

Have a look at Triggered and Enabled subsystem, when you respond just post the output signal scope that you would like to achieve for the specified inputs.

Answer 1

[Dongxu Guo]

It seems that without any delay in the feedback loop, some kind of algebraic loop was introduced and caused some unexpected error. After I added a transport delay block in the feedback loop, and set the simulation time step small enough, everything works fine.