Are RISC-V processors supported by Embedded Coder?

I want to generate code for a RISC-V processor. Is it possible to configure Embedded Coder for RISC-V?

Answer 1

[Jack Ferrari]

Yes, you can specify the word sizes for RISC-V using the built-in RISC-V device details in the Hardware Implementation section of the Configuration Set (as shown below.)

The C standard does not fully specify integer word sizes so this will ensure that the generated C/C++ code will have the same numerical results on the target as it had in the model simulation.

The generated algorithm code can then be integrated and plugged into your embedded software framework and scheduler as you would do with hand code for your production hardware.

If you desire complete support of a particular RISC-V Board, that is directly generated from Embedded Coder with I/O drivers, scheduler, profiling, and more, you can request MathWorks consulting services to create a custom Embedded Target solution.

[Walter Roberson]

The C standard has minimum word sizes for the different integer types, but those minimums were set back in the days that 16 bit and 32 bit processors were common, so the minimum sizes of the C standards are not all that useful these days, except possibly in some small-system embedded processor work.

C++ also defines minimum sizes, with lengths that are more relevant to most people.

[svanimisetti]

Thanks for this post Jack! Is there a BSP for RV32I-based boards such as SiFive HiFive1 RevB? Or does this work with any RISC-V board?

[Jack Ferrari]

@svanimisetti While we do not have a BSP specific to that board, the IDE should be able to call code generated with Embedded Coder with its own scheduler. The code should work on any RISC-V board.

[svanimisetti]

Thanks for confirming!