Info
This question is closed. Reopen it to edit or answer.
How to reprogram the FPGA using the previously generated bitstream
1 view (last 30 days)
Show older comments
I am using HDL Workflow Advisor to program the FPGA on the ZedBoard.
The problem is, when I close the Workflow Advisor window, I have to re-synthesize the design, even if I do not change it. Is there a way to reprogram the FPGA using the previously generated bitstream without going through the Workflow Advisor again?
1 Comment
Long Wang
on 17 Nov 2017
Actually this would also be my question :-) Additionally I would like to know, how to use JTAG to download the bitstream to Zedboard. Hopefully after two years, there will be an answer.
Answers (0)
This question is closed.
See Also
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!