Adding one signal to an existing bus without nesting or unfolding

What I want to do is pretty simple: add a signal to an existing bus.

But: Putting an existing bus and the respective signal in a bus creator results in nested bus signals and inconsistent names across the model.

One messy way: unfold the existing bus with n signals in a bus selector, put the additional signal and the n signals in an n+1 size buscreator.

A complicated way: initially create the bus with all signals and put in dummy values, then use the bus assignment block.

Shouldn't there be an easier way?

Answer 1

[AutoEng]

I know it's necroposting, but in 2020 I still missing feature to uppend existing virtual bus with new signals, forming a new virtual bus.

For myself, based on this answer, I have created a dynamic masked subsystem which do a "messy way" from the question automatically.

But my block needs ctrl-D to update what is not so convenient to do each time.

Probably a better way exists. So any enchancements are highly appreciated!