up sample Simulink doesn't implement rate convertion on hdl coder

Hi all ,

we are trying to implement a up sample implemantation via the hdl coder for xilinx chip but we notice something very weird .

let's assume that our data source is on 51.2 MHz and we want to use upsample (not reapeter) by 3 in order to achieve 153.6MHz data rate .

in the simulink simulation it's look like it working ok but if we use the hdl workflow advisor in order to make form our upsample block a custom ip for generic xilinx platform , we saw on the ip clock\timing report that the output rate is the same as the input rate meaning 51.2MHz ( and not 153.6 MHz like it supposed to be )

we configured the upsample block to Input processing = Element as channels(sample based) meaning that the rate options is = Allow multirate processing (and the sample offset is 0 and the intial conditions is also 0)

what can be the problem and how we can solve it ?

with best regards.

Dror & Raz

Answer 1

[Kiran Kintali]

Please share your model. I do not see any such errors with a basic model with your sample settings.