CCSDS LDPC Encoder

Encode data with (8160,7136) LDPC code specified in CCSDS telemetry standard

Since R2025a

• 

Libraries:
Wireless HDL Toolbox / Error Detection and Correction

Description

The CCSDS LDPC Encoder block encodes data with (8160,7136) low-density parity-check (LDPC) code specified in the Consultative Committee for Space Data Systems (CCSDS) Telemetry standard. The block accepts data bits and a stream of control signals as inputs. The block outputs encoded bits, a stream of control signals, and a signal that indicates when the block is ready to accept new inputs.

The block supports scalar input and vector inputs of size 8. The block provides an architecture suitable for HDL code generation and hardware deployment. You can use this block in a CCSDS transmitter for satellite communication. To know more about CCSDS Telemetry standard, see [1]

Examples

Encode Data with LDPC Code in CCSDS Telemetry Standard

Use CCSDS LDPC Encoder block to encode data bits with (8160,7136) LDPC code.

• Open Script

Ports

Input

data — Input data bits

scalar | column vector

Input data bits, specified as a Boolean scalar or an eight-element Boolean column vector.

Data Types: Boolean

ctrl — Control signals accompanying sample stream

samplecontrol bus

Control signals accompanying the sample stream, specified as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

• start — Indicates the start of the input frame

• end — Indicates the end of the input frame

• valid — Indicates that the data on the input data port is valid

For more details, see Sample Control Bus.

Data Types: bus

Output

data — Encoded output data bits

scalar | vector

Encoded output data bits, returned as a Boolean scalar or an eight-element Boolean column vector. The output data type is same as the input data type.

Data Types: Boolean

ctrl — Control signals accompanying sample stream

samplecontrol bus

Control signals accompanying the sample stream, returned as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

• start — Indicates the start of the output frame

• end — Indicates the end of the output frame

• valid — Indicates that the data on the output data port is valid

For more details, see Sample Control Bus.

Data Types: bus

nextFrame — Block ready indicator

scalar

Block ready indicator, returned as a Boolean scalar.

The block sets this signal to 1 when the block is ready to accept the start of the next frame. If the block receives an input ctrl.start signal while nextFrame is 0, the block discards the frame in progress and begins processing the new data.

Data Types: Boolean

Algorithms

This figure shows the architecture block diagram of the CCSDS LDPC Encoder block. For each batch of 511 input bits, the row counter increases by one. Using the current row count, the Generator Matrix look-up table (LUT) provides the corresponding row of the matrix. Each input bit is then XORed with the parity bits, which are circularly shifted by one position. This operation is repeated for the entire set of input bits.

Latency

The latency of the block varies based on the type of input. Because the latency varies, use the nextFrame control signal output port to determine when the block is ready for a new input frame.

This figure shows a sample output and latency of the CCSDS LDPC Encoder block for a scalar input. The latency of the block is 5 clock cycles.

This figure shows a sample output and latency of the CCSDS LDPC Encoder block for an eight-element column vector input. The latency of the block is 11 clock cycles.

Performance

The performance of the synthesized HDL code varies with the target and synthesis options. The performance also varies based on the type of input.

This table shows the resource and performance data synthesis results of the block for a scalar and vector inputs for (8160,7136) LDPC configuration. The generated HDL targets to the AMD^® Zynq^® UltraScale+™ MPSoC - ZCU102 Evaluation Board.

Input Type	Slice LUTs	Slice Registers	Block RAMs	Maximum Frequency in MHz
Scalar	3152	3157	0	724.6
Vector	7152	2143	0	573.39

References

[1] TM Synchronization and Channel Coding. Recommendation for Space Data System Standards. CCSDS 131.0-B-3. Blue Book. Issue 3. Washington, D.C.: CCSDS, September 2017.

[2] TM Synchronization and Channel Coding. Summary of Concept and Rationale CCSDS 130.1-G-3. Green Book. Issue 3, June 2020.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Restrictions

You cannot generate HDL for this block inside a Resettable Synchronous Subsystem (HDL Coder).

Version History

Introduced in R2025a