To detect hidden design errors in your model early in the verification process, use design error detection analysis. This tutorial shows how to perform design error detection analysis, review the analysis results, and then fix the identified design errors.
Consider a controller that has three sensor inputs:
SensorC. The controller algorithm
operates according to the equation:
The algorithm is modeled as:
To perform design error detection analysis:
Open the model sldvexControllerIntegerOverflow.
On the Design Verifier tab, in the Mode section, select Design Error Detection.
Click Error Detection Settings. In the Configuration Parameters dialog box, on the Design Verifier > Design Error Detection pane, select the checks that you want to perform.
To perform design error detection analysis, on the Design Verifier tab, click Detect Design Errors. The software analyzes the model for design errors and displays the results in the Results Summary window. The results indicate that three out of six objectives were falsified.
You can review the analysis results by highlighting the results on the model and reviewing the analysis report.
On the Design Verifier tab, in the Review Results section, click Highlight in Model.
The model items highlighted in red are the objectives that resulted in errors. You can replicate the error by simulating the test case.
Select the Sum block. The Results Inspector window displays the integer overflow objectives of the Sum block.
To debug the integer overflow error, click View test case. The harness model and the Signal Builder block open.
When the input value of
160, the Sum block output
overflows. The accumulator data type of the Sum block
is set to an incorrect integer value of
results in overflow errors and division by zero errors on the
downstream Divide block.
To view the HTML report, in Review Results, click HTML Report. The Design Error Detection Objectives section lists the objectives of each model items and their description.
In the tutorial model, the design error detection analysis found integer overflow and division by zero errors in the model. The errors were caused due to a mismatch in the integer data type.
To fix the errors, change the Accumulator data type to
to handle the range of possible signal values. Select the Sum block,
and set Accumulator data type to uint16. When you rerun the
design error detection analysis, the Results Summary window reports that
6/6 objectives are valid. When you simulate the test case for
the Sum, observe that the test case resolves the error.