Design error detection is a Simulink® Design Verifier™ analysis mode that detects the following types of errors:
Out of bound array access
Integer or fixed-point data overflow
Division by zero
Errors in floating-point usage (
Intermediate signal values that are outside the specified minimum and maximum values
Data store access violations
Specified block input range violations
High-Integrity Systems Modeling checks
Before you simulate your model, analyze your model in design error detection mode to find and diagnose these errors. Design error detection analysis determines the conditions that cause the error, helping you identify possible design flaws. Design error detection analysis also computes a range of signal values that can occur for block outports and Stateflow® local data in your model.
Model objects that have decision or condition outcomes receive dead logic detection.
After the analysis, you can:
Click individual blocks to view the analysis results for that block.
Create a harness model containing test cases that demonstrate the errors.
Create an analysis report that contains detailed results for the entire model.