Check for dead logic
R2026bCheck ID:
mathworks.sldv.deadlogic
Identify logic that stays inactive during simulation.
Description
This check identifies portions of your model that stay inactive during simulation.
You can run a more detailed analysis that identifies both dead logic and active logic using Simulink® Design Verifier™ design error detection. For more information, see Detect Dead Logic Caused by an Incorrect Value (Simulink Design Verifier).
Following the recommendations of this check increases the likelihood of generating MISRA™ C:2012 compliant code for embedded applications, as well as code that complies with the CERT® C and CWE™ standards.
Results and Recommended Actions
| Result | Recommended Action |
|---|---|
| Failed, model incompatible | Resolve the model incompatibility. See:
Also see Handle Model Complexities with Automatic Stubbing (Simulink Design Verifier). |
| Dead logic found in model | Simulink Design Verifier proved that these decision and condition outcomes cannot occur and are dead logic in the model. Dead logic can also be a side effect of specified constraints on parameters or specified minimum and maximum constraints on input ports. In rare cases, dead logic can result from approximations performed by Simulink Design Verifier. It is possible that there are objectives that this analysis did not decide. To extend the results of this
analysis, use Simulink
Design Verifier design error detection to also identify active logic.
In the Configuration Parameters dialog box, on the Design Verifier > Design Error Detection pane, select Dead logic
(partial). Alternatively, set
|
| Dead logic not found in model | Simulink
Design Verifier did not find dead logic in the model. It is possible that
there are objectives that this analysis did not decide. To extend the
results of this analysis, use Simulink
Design Verifier design error detection to also identify active logic. In
the Configuration Parameters dialog box, on the Design Verifier > Design Error Detection pane, select Dead logic (partial) or
set DVDetectDeadLogic and
DVDetectActiveLogic to "on". |
Capabilities and Limitations
Does not run on library models.
Analyzes content in masked subsystems. The input parameter Look inside masks is always set to
all. You can use a filter to exclude specific subsystems. For more information, see Filter Objectives by Using Simulink Design Verifier Filter Explorer (Simulink Design Verifier).Analyzes content of library-linked blocks. The input parameter Follow links is always set to
on.Does not support exclusions.
Tips
If a dead logic warning results from a parameter that is intended to be tunable (for
example, a parameter with an enumerated data type), configure that parameter for tuning
in Simulink
Design Verifier. When the parameter is tunable, the dead logic check considers alternative
parameter values and can determine whether a previously dead branch is reachable. To
configure parameters, use the Automatically infer parameter
specification setting or the Parameter table in
the Configuration Parameters dialog box to specify possible enumerated values. Then, run
the Check for dead logic analysis on the model. For
more information, see Create Parameter Configuration for Simulink Design Verifier Analysis (Simulink Design Verifier).
See Also
MISRA C:2012: Rule 2.1
CERT C, MSC07-C
CWE, CWE-561
Secure Coding (Embedded Coder)
Detect Dead Logic Caused by an Incorrect Value (Simulink Design Verifier)
Design Verifier Pane: Design Error Detection (Simulink Design Verifier)
hisl_0101: Prevent operations that result in dead logic to improve code compliance
