Detect Dead Logic

Check ID: mathworks.sldv.deadlogic

Identify logic that stays inactive during simulation.

Description

This check identifies portions of your model that stay inactive during simulation.

You can run a more detailed analysis that identifies both dead logic and active logic using Simulink^® Design Verifier™ design error detection. For more information, see Detect Dead Logic Caused by an Incorrect Value (Simulink Design Verifier).

Following the recommendations of this check increases the likelihood of generating MISRA C:2012 compliant code for embedded applications, as well as code that complies with the CERT C and CWE standards

Results and Recommended Actions

Result Recommended Action

Failed, model incompatible

Result	Recommended Action
Failed, model incompatible	Resolve the model incompatibility. See: Supported and Unsupported Simulink Blocks in Simulink Design Verifier (Simulink Design Verifier) Support Limitations for Model Blocks (Simulink Design Verifier) Support Limitations for Simulink Software Features (Simulink Design Verifier) Support Limitations for Stateflow Software Features (Simulink Design Verifier) Support Limitations for MATLAB for Code Generation (Simulink Design Verifier) Also see Handle Incompatibilities with Automatic Stubbing (Simulink Design Verifier).
Dead logic found in model	Simulink Design Verifier proved that these decision and condition outcomes cannot occur and are dead logic in the model. Dead logic can also be a side effect of specified constraints on parameters or specified minimum and maximum constraints on input ports. In rare cases, dead logic can result from approximations performed by Simulink Design Verifier. It is possible that there are objectives that this analysis did not decide. To extend the results of this analysis, use Simulink Design Verifier design error detection to also identify active logic. From the Simulink Editor, select Apps > Design Verifier > Settings. In the Configuration Parameters window, from Design Verifier > Design Error Detection pane, select Dead logic (partial) or set `DVDetectDeadLogic` and`DVDetectActiveLogic` to `on`.
Dead logic not found in model	Simulink Design Verifier did not find dead logic in the model. It is possible that there are objectives that this analysis did not decide. To extend the results of this analysis, use Simulink Design Verifier design error detection to also identify active logic. From the Simulink Editor, select Apps > Design Verifier > Settings. In the Configuration Parameters window, from Design Verifier > Design Error Detection pane, select Dead logic (partial) or set `DVDetectDeadLogic` and `DVDetectActiveLogic` to `on`.

Resolve the model incompatibility. See:

Supported and Unsupported Simulink Blocks in Simulink Design Verifier (Simulink Design Verifier)
Support Limitations for Model Blocks (Simulink Design Verifier)
Support Limitations for Simulink Software Features (Simulink Design Verifier)
Support Limitations for Stateflow Software Features (Simulink Design Verifier)
Support Limitations for MATLAB for Code Generation (Simulink Design Verifier)

Also see Handle Incompatibilities with Automatic Stubbing (Simulink Design Verifier).

Dead logic found in model Simulink Design Verifier proved that these decision and condition outcomes cannot occur and are dead logic in the model. Dead logic can also be a side effect of specified constraints on parameters or specified minimum and maximum constraints on input ports. In rare cases, dead logic can result from approximations performed by Simulink Design Verifier. It is possible that there are objectives that this analysis did not decide. To extend the results of this analysis, use Simulink Design Verifier design error detection to also identify active logic. From the Simulink Editor, select Apps > Design Verifier > Settings. In the Configuration Parameters window, from Design Verifier > Design Error Detection pane, select Dead logic (partial) or set DVDetectDeadLogic andDVDetectActiveLogic to on.

Dead logic not found in model Simulink Design Verifier did not find dead logic in the model. It is possible that there are objectives that this analysis did not decide. To extend the results of this analysis, use Simulink Design Verifier design error detection to also identify active logic. From the Simulink Editor, select Apps > Design Verifier > Settings. In the Configuration Parameters window, from Design Verifier > Design Error Detection pane, select Dead logic (partial) or set DVDetectDeadLogic and DVDetectActiveLogic to on.