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UCIe 1.0 Transmitter/Receiver IBIS-AMI Model

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This example shows how to create IBIS-AMI models for Universal Chiplet Interconnect Express (UCIe) Version 1.0 transmitter and receiver for clock and data using the library blocks in SerDes Toolbox. The IBIS-AMI models generated by this example utilize IBIS Clock Forwarding functionality which can be simulated in Parallel Link Designer from Signal Integrity Toolbox and conform to the UCIe specification.

Create Tx and Rx Models for Single-Ended Data and Differential Clock Signals

This example shows how to create transmitter and receiver for clock and data for a UCIe 1.0 system using the SerDes Designer app to later create IBIS-AMI models. You will see how the system can then be exported to Simulink® for further customization. You can configure the various settings using values from the UCIe specification (see reference section below) in both the SerDes Designer app and in Simulink.

Part 1: Setup Tx and Rx Models for Single-Ended Data in SerDes Designer

You can load the system model for the UCIe 1.0 data signal by typing the following command in the MATLAB® command window to open the SerDes Designer model ucie1_txrx_data_se.mat:

>> serdesDesigner('ucie1_txrx_data_se');

Configuration Setup

  • Symbol Time is set to 31.25 ps representing a data rate of 32 GT/s with NRZ modulation, which equates to a Nyquist frequency of 16GHz.

  • Target BER is set to 1e-12.

  • Samples per Symbol is set to 16 (default).

  • Modulation is set to NRZ.

  • Signaling is set to Single-ended (UCIe data signals utilize single-ended signaling and this will be part of the IBIS-AMI model).

Transmitter Model Setup

The Tx incorporates a VGA block to provide Gain adjustment:

  • Gain is 0.575 (from Table 1-3).

  • Note: Additional Gain presets can be configured to be selectable options later in this example when the system is exported to Simulink.

Tx FFE is defined as having 2 cursors: one main tap and one post-tap. The initial setting is as follows:

  • Tap Weights is [1 0] (Setting 1 from Table 5-3).

  • Note: Specific tap presets can be configured to be selectable options later in this example when the system is exported to Simulink.

The Tx AnalogOut block is configured as follows:

  • Voltage is 1.0 V (The VGA block will control Gain adjustment).

  • Rise time is 12.5 ps (0.4UI from Table 5-2).

  • R (output resistance) is 30 Ohms (Table 5-2).

  • C (capacitance) is 0.125 pF (Table 5-2).

Channel Model Setup

  • Channel loss is set to 6 dB (Note: this can vary given the specific UCIe Channel Reach of your system).

  • Single-ended impedance is set to 50 Ohms.

  • Target Frequency is set to the Nyquist frequency of 16 GHz, which corresponds to 32GT/s with modulation set to NRZ.

Receiver Model Setup

The Rx AnalogIn block is configured as follows:

  • R (input resistance) is 50 Ohms (Table 5-4).

  • C (capacitance) is 0.125 pF (Table 5-4). 

The Rx CTLE block set up as follows:

  • 4 configurations (0 to 3) and the associated GPZ Matrix is derived from the CTLE example transfer equation provided (Section 5.4.3).

  • Note: A dedicated DFEClkFwd block that supports IBIS Clock Forwarding functionality will be added later after exporting to Simulink.

Receiver Model Setup: Find the CTLE GPZ Matrix

You can see from the loaded model, that the Rx CTLE block contains multiple configurations to accommodate the dynamic range of this peaking filter. This is implemented using a gain-pole-zero matrix based on an example transfer function for a CTLE provided by the specification as follows:

Where

  • wp2 = 2pi*DataRate,

  • wp1 = 2pi*DataRate/4,

  • and ADC is the DC Gain.

The following code block shows you one method to find a GPZ Matrix for the CTLE block using the transfer equation.

DCgain = 0:3;
ADC = 10.^(-DCgain/20);

datarate = 32e9; %Hz
p1 = datarate/4;
p2 = datarate;
wp1 = 2*pi*p1;
wp2 = 2*pi*p2;

f = linspace(0.1,20e9,1001);
w = 2*pi*f;
s = 1j*w;

H = zeros(length(ADC),length(f));

for ii = 1:length(ADC)
    H(ii,:) = wp2.*(s + ADC(ii)*wp1)./((s + wp1).*(s + wp2));
end

figure(1)
ax1(1) = subplot(211);
semilogx(f,db(H))
grid on
xlabel('Hz')
ylabel('dB')
title('Reference CTLE from UCIe 1.0, Section 5.4.3')
ax1(2) = subplot(212);
semilogx(f,unwrap(angle(H)))
grid on
xlabel('Hz')
ylabel('Radians')
linkaxes(ax1,'x')

%Define z1 for gpz matrix:
z1 = ADC*p1;
%Define gpz matrix:
gpz = zeros(length(ADC),4);
gpz(:,1) = -DCgain;
gpz(:,2) = -p1;
gpz(:,3) = -z1;
gpz(:,4) = -p2;

You can verify that the CTLE transfer function embedded in the system object matches the GPZ-matrix expression of that transfer function by using a visualization overlay:

myctle = serdes.CTLE('Specification','GPZ Matrix','GPZ',gpz)
myctle = 
  serdes.CTLE with properties:

   Main
             Mode: 2
    Specification: 'GPZ Matrix'
              GPZ: [4x4 double]
      SliceSelect: 0
     ConfigSelect: 0

  Use get to show all properties


[~,H2]=response(myctle,f);
figure(2),clf,plot(f,db(H2),'r'),hold all,plot(f,db(H2),'b')

Note: You can also visualize the response by clicking the Add Plots and selecting CTLE Transfer Function from the drop-down menu.

You are now ready to export to Simulink for further customization, such as adding a dedicated DFEClkFwd block that supports IBIS Clock Forwarding and an entry for additional UCIe metrics such as Receiver Sensitivity. These topics will be covered later in this example.

Part 2: Export Single-Ended Data Models to Simulink

Next in SerDes Designer, export the model ucie1_txrx_data_se to Simulink to allow enhanced customization of each portion of the system.

Configure Data Transmitter Subsystem

The Tx subsystem contains a VGA block and an FFE block. You can configure the options available for controlling the VGA block by modifying its IBIS-AMI Parameter for Gain in the IBIS-AMI Manager as follows:

  • Description: VGA Gain: Data Lane Tx Swing (single ended) from Table 5-2, UCIe specification 1.0, Revision 1.1.

  • Usage: In

  • Type: Float

  • Format: List

  • Default: 0.575

  • List values: [0.4 0.575 0.75]

  • List_Tip values: ["0.4V se" "0.575V se" "0.75V se"]

Next, you can add the capability to select FFE presets with the following steps:

In the IBIS-AMI Manager, open the AMI - Tx tab. Then click on the FFE and create a new parameter "ConfigSelect:"

In the edit dialog, enter the following:

  • Parameter name: ConfigSelect

  • Description: Tx FFE Tap Weights Configuration

  • Usage: In

  • Type: Integer

  • Format: List

  • Default: 0

  • List values: [-1 0 1]

  • List_Tip values: ["User Defined" "P0" "P1"]

Then set the Current Value to P0.

Next, look under the FFE block, and create a new MATLAB function that can switch based on the new IBIS-AMI parameter as follows:

  • Click on the canvas and create a MATLAB function named TxFFEPreset_UCIe_v1

  • The following code block shows an option for how to provide a selector within the IBIS-AMI model:

function TapWeightsOut = TxFFEPreset_UCIe_v1(TapWeightsIn, ConfigSelect)

% Derived from UCIe Version 1.0 Revision 1.1 specification, Tx FFE.

switch ConfigSelect

case -1 % User defined tap weights

TapWeightsOut = TapWeightsIn;

case 0 % Preset Configuration: P0

TapWeightsOut = [0.774 -0.226];

case 1 % Preset Configuration: P1

TapWeightsOut = [1.0 0];

otherwise

TapWeightsOut = TapWeightsIn;

end

end

  • Connect the FFEParameter.TapWeights block to the TapWeightsIn input to the function TxFFEPreset_UCIe_v1.

  • Connect the FFEParameter.ConfigSelect block to the ConfigSelect input to the function TxFFEPreset_UCIe_v1.

  • Connect the output TapWeightsOut of the TxFFEPreset_UCIe_v1 block to the TapWeights input of the FFE block.

You can see a diagram below of the completed subsystem:

Configure Data Receiver Subsystem

Next, you will need to add the capability of IBIS Clock Forwarding support in the receiver subsystem. This also requires adding the IBIS AMI Reserved_Parameter "Rx_Use_Clock_Input." This is enabled automatically by the DFEClkFwd block. You can add this block in the following steps:

  • Double click on the Rx block

  • Click on the Library Browser

  • Navigate to the SerDes Toolbox section

  • And add an instance of the block DFEClkFwd

  • Then complete the path from WaveIn to CTLE block to DFEClkFwd block to WaveOut.

Next, set the DFE Mode to "Off" because we will not be using DFE feature of this block in a UCIe interface (Note: You will be using the IBIS-Clock-Forwarding feature provided by the DFEClkFwd block):

Note: you can ignore the various DFE tap settings, as these are defaults for the app and will not be used when set to "Off."

Then in the CDR tab, enter the following setting for receiver sensitivity:

  • Sensitivity (V) to 0.02 (UCIe Specification).

  • Note: other CDR entries can be left to default settings.

Then under the Configuration Block, open the IBIS-AMI Manager, and click on the AMI - Rx tab. A new Reserved_Parameter "Rx_Use_Clock_Input" has been added. You can set the drop-down for Current Value to "Wave."

Note: The DFE is set to off, so you can set the option Hidden to Enabled for the following:

  • DFEClkFwd.Mode

  • DFEClkFwd.ReferenceOffset

  • DFEClkFwd.PhaseOffset

  • DFEClkFwd.TapWeights

Configure Data Stimulus

You can navigate to the Stimulus block and set the Waveform creation method to Serial PRBS:

Note: the default for Number of symbols is 20000, but you can utilize a smaller value to speed-up simulation run times.

Note: if you click on the "Clock Forwarding" tab in the Stimulus window, you can see that the Current State is listed as "Wave" based on your selection above for Rx_Use_Clock Input in the IBIS-AMI Manager. You can also configure the following settings:

  • Generate Clock or Strobe Waveform: Enabled

  • Include Analog Channel model in clock waveform: Enabled

  • Pattern Type: Clock Pattern

  • Delay (s): 15.625e-12

  • Note: You can configure Delay value to optimize the location of the clock PDF in the plot.

Run the system in Simulink.

Generate and Export IBIS-AMI Models for Single-Ended Data

Next you will see how to generate IBIS-AMI compliant model executables, IBIS and AMI files.

Open the Block Parameter dialog box for the Configuration block and click on the SerDes IBIS-AMI Manager button. In the IBIS tab inside the SerDes IBIS-AMI manager dialog box, the analog model values are converted to standard IBIS parameters that can be used by any IBIS-compliant simulator. In the AMI-Tx and AMI-Rx tabs in the SerDes IBIS-AMI manager dialog box, the reserved parameters are listed first followed by the model specific parameters following the format of a typical AMI file.

Export IBIS-AMI Models

Select the Export tab in the SerDes IBIS-AMI manager dialog box.

  • Update the Tx model name to ucie_data_cf_tx

  • Update the Rx model name to ucie_data_cf_rx

  • Note that the Tx and Rx corner percentage is set to 10%. This will scale the min/max analog model corner values by +/-10%.

  • Verify that Dual model is selected for both the Tx and the Rx. This will create model executables that support both Statistical (Init) and Time Domain (GetWave) analysis.

  • Set the Tx model Bits to ignore value to 2 since there is 1 main tap and 1 post tap in the Tx FFE.

  • Set the Rx model Bits to ignore value to 1000 as a reasonable value to enable Rx equalizer blocks to settle during time domain simulations.

  • Verify that Both Tx and Rx are set to Export and that all files have been selected to be generated (IBIS file, AMI files, .dll files [Windows] and/or .so files [Unix/Linux]).

  • Set the IBIS file name to be ucie_data_cf.ibs

You can now observe the IBIS-AMI manager looks as follows, where your system is ready to export IBIS-AMI models.

  • Once verified, you can click the Export button to generate models in the Target directory.

Part 3: Setup Tx and Rx Models for Differential Clock in SerDes Designer

You can load the system model for clock by typing the following command in the MATLAB® command window to open the SerDes Designer model ucie1_txrx_clk_ds.mat:

>> serdesDesigner('ucie1_txrx_clk_ds');

Configuration Setup

  • Symbol Time is set to 31.25 ps representing a data rate of 32 GT/s with NRZ modulation, which equates to a Nyquist frequency of 16GHz.

  • Target BER is set to 1e-12.

  • Samples per Symbol is set to 16 (default).

  • Modulation is set to NRZ.

  • Signaling is set to Differential (UCIe clock signals utilize differential signaling and this will be part of the IBIS-AMI model).

Transmitter Model Setup

The Tx incorporates a VGA block to provide Gain adjustment:

  • Gain is 0.575.

  • Note: Additional Gain presets can be configured to be selectable options later in this example when the system is exported to Simulink.

The Tx AnalogOut block is configured as follows:

  • Voltage is 1.0 V.

  • Rise time is 12.5 ps.

  • R (output resistance) is 30 Ohms.

  • C (capacitance) is 0.125 pF.

Channel Model Setup

  • Channel loss is set to 6dB (Note: this can vary given the specific UCIe Channel Reach of your system).

  • Differential impedance is set to 100 Ohms.

  • Target Frequency is set to the Nyquist frequency of 16 GHz, which corresponds to 32GT/s with modulation set to NRZ.

Receiver Model Setup

The Rx AnalogIn block is configured as follows:

  • R (input resistance) is 50 Ohms (Table 5-4).

  • C (capacitance) is 0.125 pF (Table 5-4).

Part 3: Exporting Models to Simulink

Part 3a: Setup Differential Clock Models

In this section, you can continue this workflow by exporting the differential clock model to Simulink first. After that point you will see the steps to setup and export the more complex single-ended data model. Each involves unique steps to enable Clock Forwarding support for IBIS-AMI models. In EDA tools, the clock and data are expected to be implemented as a pair to support Clock Forwarding simulation.

Click on Export in the toolstrip to launch Simulink with the differential clock system model ucie1_txrx_clk_ds.

Configure Clock Transmitter Subsystem

You can look at the components of the Tx subsystem by double-clicking on the Tx block. You will see there is a VGA block exported from SerDes Designer:

You can configure the options available for controlling the VGA block by modifying its IBIS-AMI Parameter in the SerDes IBIS-AMI Manager for Gain as follows:

  • Description: VGA Gain: clock output scaled by factor of 2 for differential signaling.

  • Usage: In

  • Type: Float

  • Format: List

  • Default: 1.15

  • List values: [0.8 1.15 1.5]

  • List_Tip values: ["0.4V se" "0.575V se" "0.75V se"]

Configure Clock Receiver Subsystem

Next you can setup the clock receiver subsystem to add a zero-crossing detector to output clock times for IBIS Clock Forwarding support. Double-click on the Rx block to open the Rx subsystem. Put down a pass-thru block. Rename the pass-thru block ClockDetect.

Go into the IBIS-AMI Manager. You can see that ClockDetect is now listed under the Model_Specific section. To support IBIS Clock Forwarding functionality, you will use a reference function DQSClock.m attached to this example.

Note: A detailed discussion of this function is beyond scope of this example, but a reference for the source example Design IBIS-AMI Models to Support Clock Forwarding is provided below.

This function utilizes specific IBIS Parameters. Navigate to the AMI - Rx tab in the IBIS-AMI Manager, and create new Parameters for the following under the Model_Specific entry for ClockDetect that was created above.

  • DQS_Preamble

  • Strobe_or_Clock

For the Parameter DQS_Preamble, create the following values:

  • Parent Node: ClockDetect

  • Parameter name: DQS_Preamble

  • Description: Number of DQS transitions to skip before outputting clock times during a DQS burst. Currently requires at least 4 DQS UI between bursts. 1tCK = 2 DQS UI.

  • Usage: In

  • Type: Integer

  • Format: List

  • Default: 0

  • List values: [0 1 2 3 4]

  • List_Tip values: ["0tCK" "1tCK" "2tCK" "3tCK" "4tCK"]

  • Current value: 0tCK

  • Hidden: Check Enabled

  • Note: The Hidden option is being selected to hard-code 0 as the default for this model- this Parameter is capable of accommodating DDR5 and other DDR or SDR standards that may utilize IBIS Clock Forwarding, but 0 is sufficient for this interface.

For the Parameter Strobe_or_Clock, create the following values:

  • Parent Node: ClockDetect

  • Parameter name: Strobe_or_Clock

  • Description: Strobe or Clock signal. A Strobe signal returns clock times every edge (DDR) while a Clock signal only returns clock times on rising edges (SDR).

  • Usage: In

  • Type: Integer

  • Format: List

  • Default: 0

  • List values: [0 1]

  • List_Tip values: ["Strobe" "Clock"]

  • Current value: Strobe

  • Hidden: Check Enabled

Now that you have created these Parameters, look under the Pass-through block and add a MATLAB Function clock to call DQSClock.m. Also place an IBIS-AMI clock_times block from the Library Browser for SerDes Toolbox. Then, you can connect the subsystem components as follows:

  • Connect WaveIn to Out

  • Connect WaveIn also to WaveIn input to the DQSClock block.

  • Connect DQS_Preamble to the PreAmble input of the DQSClock block.

  • Connect Strobe_or_Clock to the DQSCK input of the DQSClock block.

  • Connect clockValid output to the clockValid input of the IBIS-AMI clock_times block.

  • Connect clockTime output to the clockTime input of the IBIS-AMI clock_times block.

Below is an example of how the subsystem should appear:

Next, set the following Block Parameters for IBIS-AMI clock_times block:

  • Enable IBIS-AMI Offset: Disabled

Note: In order to properly output the clock crossing times to support Clock Forwarding, you must un-check Enable IBIS-AMI Offset. Further explanation is provided in the example Design IBIS-AMI Models to Support Clock Forwarding in the reference section below.

Configuration Block Settings for Clock Subsystem

You can confirm the Configuration block settings are as follows:

  • Symbol time (s): 31.25e-12

  • Samples per symbol: 16

  • Target BER: 1e-12

  • Modulation: NRZ

  • Signaling:Differential

  • Eye Diagram Clock: Clocked

Configure Clock Stimulus

You can configure the Stimulus block such that it is representative of a clock signal as follows:

  • Waveform Creation method: Binary Pattern

  • Binary pattern: [0 1 0 1 0 1 0 1]

You can now run the system in Simulink.

Note: Given that a binary pattern is being implemented, it is recommened to set the option in the Time Domain plot for "Symbols per trace" to 1 to optimize visualization.

Generate and Export IBIS-AMI Models for Differential Clock

Open the Block Parameter dialog box for the Configuration block and click on the SerDes IBIS-AMI Manager button. In the IBIS tab inside the SerDes IBIS-AMI manager dialog box, the analog model values are converted to standard IBIS parameters that can be used by any industry standard simulator. In the AMI-Tx and AMI-Rx tabs in the SerDes IBIS-AMI manager dialog box, the reserved parameters are listed first followed by the model specific parameters, according to the format rules of an IBIS-AMI file provided by the IBIS specification.

Export IBIS-AMI Models

Select the Export tab in the SerDes IBIS-AMI manager dialog box.

  • Update the Tx model name to ucie_clk_cf_tx

  • Update the Rx model name to ucie_clk_cf_rx

  • Note that the Tx and Rx corner percentage is set to 10%. This will scale the min/max analog model corner values by +/-10%.

  • Verify that Dual model is selected for both the Tx and the Rx. This will create model executables that support both statistical (Init) and time domain (GetWave) analysis.

  • Set the Rx model Bits to ignore value to 1000 as a reasonable value to enable Rx blocks to settle during time domain simulations.

  • Verify that Both Tx and Rx are set to Export and that all files have been selected to be generated (IBIS file, AMI files, .dll files [Windows] and/or .so files [Unix/Linux]).

  • Set the IBIS file name to be ucie_clk_cf.ibs

You can now observe the IBIS-AMI manager looks as follows, where your system is ready to export IBIS-AMI models.

  • Once verifed, you can click the Export button to generate models in the Target directory.

Test Generated IBIS-AMI Models

The UCIe 1.0 transmitter and receiver IBIS-AMI models are now complete and ready to be utilized within Parallel Link Designer from Signal Integrity Toolbox, or any industry EDA tool capable of IBIS-AMI simulation with support for IBIS Clock Forwarding.

References

[1] UCIe Version 1.0 Specification, Revision 1.1: https://www.uciexpress.org/

[2] IBIS 7.2 Specification, including definition of Clock Forwarding implementation in IBIS-AMI models: https://ibis.org/ver7.2/ver7_2.pdf

See Also

SerDes Designer | FFE | CTLE | CDR

Related Topics

References

[1] UCIe Version 1.0 Specification, Revision 1.1: https://www.uciexpress.org/

[2] IBIS 7.2 Specification, including definition of Clock Forwarding implementation in IBIS-AMI models: https://ibis.org/ver7.2/ver7_2.pdf

See Also

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Related Topics