displayCaptureCondition

Display overall capture condition

Since R2024a

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Syntax

displayCaptureCondition(hub)
displayCaptureCondition(hub,DataCaptureName=dataCaptureIPName)

Description

Add-On Required: This feature requires the HDL Verifier Support Package for AMD FPGA and SoC Devices add-on.

displayCaptureCondition(hub) displays the signal value comparisons and logical operator that define the overall capture condition for the first data capture IP. hub is a customized data capture object.

example

displayCaptureCondition(hub,DataCaptureName=dataCaptureIPName) displays the signal value comparisons and logical operator that define the overall capture condition for a data capture IP specified by dataCaptureIPName.

Examples

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This example uses a customized data capture hub object, hub, that connects with two data capture IPs. The first data capture IP is datacapture1 and the second data capture IP is datacapture2. Each IP defines two signals for both trigger and data capture. Signal A is 1 bit and signal B is 8 bits.

Enable capture condition logic for the datacpture1 IP.

setEnableCaptureCtrl(hub,true);

To enable capture condition logic, you must select the Include capture condition logic parameter while generating the data capture IPs using the FPGA Data Capture Component Generator tool.

Enable capture condition logic for the datacpture2 IP.

setEnableCaptureCtrl(hub,true,DataCaptureName="datacapture2");

Set up a capture condition to capture data when the FPGA detects a high value on signal A at the same time as signal B is greater than 7. Set this condition for the datacapture1 IP.

setCaptureCondition(hub,'A',true,'High');
setCaptureCondition(hub,'B',true,7);
setCaptureConditionComparisonOperator(hub,'B','>');

Combine comparisons of signals A and B into an overall capture condition using an AND operator.

setCaptureConditionCombinationOperator(hub,'AND');

Set a similar capture condition for the datacapture2 IP.

setCaptureCondition(hub,'A',true,'High',DataCaptureName="datacapture2");
setCaptureCondition(hub,'B',true,7,DataCaptureName="datacapture2");
setCaptureConditionComparisonOperator(hub,'B','>', ...
DataCaptureName="datacapture2");
setCaptureConditionCombinationOperator(hub,'AND', ...
DataCaptureName="datacapture2");

Display the overall capture condition for the datacapture1 IP.

displayCaptureCondition(hub);
The capture condition is:
A==High and B>7

Display the overall capture condition for the datacapture2 IP.

displayCaptureCondition(hub,DataCaptureName="datacapture2");
The capture condition is:
A==High and B>7

Input Arguments

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Data capture hub object that interacts with each data capture IP, specified as a dataCaptureHub object.

Name of the data capture IP, specified as a character vector or string scalar. The default value for this argument is "generatedIPName1", where generatedIPName1 is the name of the first data capture IP set by the Generated IP name parameter of the FPGA Data Capture Component Generator tool.

Version History

Introduced in R2024a

See Also

Objects

Tools