Use FPGA data capture to observe signals from your design while the design is running on the FPGA. This feature captures a window of signal data from the FPGA and returns the data to MATLAB® or Simulink®. To capture the signals, HDL Verifier™ generates an IP core that you must integrate into your HDL project and deploy to the FPGA along with the rest of your design. HDL Verifier also generates an app, System object™, and Simulink model that communicate with the FPGA and return the data to MATLAB or Simulink.
To capture FPGA data:
Generate customized components and an IP core. Specify port names and sizes for the generated IP. These ports connect to the signals you want to capture, and the signals you want to use as triggers to control when the capture occurs.
Integrate the generated IP into your FPGA design and deploy the design to your FPGA board. This step is automated when using HDL Workflow Advisor.
Use the generated app, System object, or Simulink model to capture data for analysis, verification, or display. You can configure a trigger condition to control when the capture occurs.
To use this feature, you must download a hardware support package for your FPGA board. More documentation for this feature is included with the support package installation. See documentation for support packages:
For information on downloading support packages, see Download FPGA Board Support Package.
High-level workflow for capturing signal data from a design running on an FPGA.