readPort

Reads output data and returns it with the port data type and dimension

Since R2020b

Syntax

data = readPort(hFPGA, portName)

data = readPort(hFPGA, portName,InterfaceID)

data,valid = readPort(hFPGA, portName)

Description

data = readPort(hFPGA, portName) reads the output data and returns this value with the port data type and dimension.

data = readPort(hFPGA, portName,InterfaceID) reads the output data from a DUT with overlapping port names by using the optionalInterfaceID argument and returns this value with the port data type and dimension.

data,valid = readPort(hFPGA, portName) reads the output data and returns this value with the port data type and dimension and an optional output whether the output data is valid.

Examples

Read Data from DUT Port Mapped to AXI4 Slave Interfaces

This example shows how to read data from the DUT ports that are mapped to AXI4 slave interfaces.

Create an fpga object with Xilinx as Vendor.

hFPGA = fpga("Xilinx")

hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the AXI4 slave interface to the hFPGA object by using the addAXI4SlaveInterface function.

%% AXI4 Slave
addAXI4SlaveInterface(hFPGA, ...
	"InterfaceID", "AXI4-Lite", ...
	"BaseAddress", 0xA0000000, ...
	"AddressRange", 0x10000);

Specify the DUT ports in the HDL IP core as an hdlcoder.DUTPort object array and then map the port to the AXI4 slave interface.

hPort = hdlcoder.DUTPort("h_out1", ...
	"Direction", "OUT", ...
	"DataType", numerictype(1,16,10), ...
	"Dimension", [1 1], ...
	"IOInterface", "AXI4-Lite", ...
	"IOInterfaceMapping", "0x104");

Map the DUT port objects to the AXI4 slave interface and then read data by using the readPort function.

mapPort(hFPGA, hPort);

data = readPort(hFPGA, "h_out1");

Read Data from DUT Port Mapped to AXI4-Stream Interfaces

This example shows how to read data from the DUT ports that are mapped to AXI4-Stream interfaces.

Create an object for the target device.

hFPGA = fpga("Xilinx")

hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the AXI4-Stream interface to the hFPGA object by using the addAXI4StreamInterface function.

addAXI4StreamInterface(hFPGA, ...
	"InterfaceID", "AXI4-Stream", ...
	"WriteEnable", true, ...
      "ReadEnable", true, ...
	"WriteFrameLength", 1024, ...
	"ReadFrameLength", 1024);

Specify the DUT port as an hdlcoder.DUTPort object array and then map the port to the AXI4-Stream interface.

hPort = hdlcoder.DUTPort("y_out", ...
	"Direction", "OUT", ...
	"DataType", numerictype(1,16,10), ...
	"Dimension", [1 1], ...
	"IOInterface", "AXI4-Stream");

Map the DUT port objects to the AXI4-Stream interface and then read data by using the readPort function.

mapPort(hFPGA, hPort);

data = readPort(hFPGA, "y_out");

Read From a DUT with Overlapping Port Names

This example shows you how to read data from a DUT with overlapping port names by using the InterfaceID argument.

Create an fpga object with Xilinx as Vendor.

hFPGA = fpga("Xilinx")

hFPGA = 

  fpga with properties:

   Top-Level Properties

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the AXI4 slave interfaces to the hFPGA object by using the addAXI4SlaveInterface function.

%% AXI4 Slave
addAXI4SlaveInterface(hFPGA, ...
	"InterfaceID", "DUT1_Registers");

Specify the DUT ports in the HDL IP core as an hdlcoder.DUTPort object array and then map the port to the AXI4 slave interface.

p1 = hdlcoder.DUTPort("myPort", ...
	"Direction", "IN", ...
	"IOInterface", "DUT1_Registers", ...
	"IOInterfaceMapping", "0x100");
mapPort(hFPGA,p1);

Add the AXI4 slave interfaces to the hFPGA object by using the addAXI4SlaveInterface function.

%% AXI4 Slave
addAXI4SlaveInterface(hFPGA, ...
	"InterfaceID", "DUT2_Registers");

Specify the DUT ports in the HDL IP core as an hdlcoder.DUTPort object array and then map the port to the AXI4 slave interface.

p2 = hdlcoder.DUTPort("myPort", ...
	"Direction", "IN", ...
	"IOInterface", "DUT2_Registers", ...
	"IOInterfaceMapping", "0x100");
mapport(hFPGA,p2);

Map the DUT port objects to the AXI4 slave interface and then read data by using the readPort function with the optional InterfaceID argument.

data = readPort(hFPGA, "DUT2_Registers", "myPort", 5);

Input Arguments

hFPGA — Target FPGA object

fpga object

fpga object for the target vendor, specified as an fpga object.

portName — DUT port name

string

DUT port name, specified as a string. You create the DUT port as an hdlcoder.DUTPort object array. Before you specify the portName, you must have mapped the port to an AXI interface by using the mapPort function.

InterfaceID — Name of FPGA interface

"" | string

Name of FPGA interface, specified as a string.

Output Arguments

data — Output data

Scalar (default) | Vector

Output data that is read from the DUT port, PortName, returned as a scalar or a vector.

valid — Read data valid true or false result

true | false | boolean

Read data valid, returned as true or false of data type boolean. This argument is only available when the ReadTimeout value is set to a finite value and the port is mapped to an AXI4-Stream interface.

Version History

Introduced in R2020b