Learn about various speed and area optimizations and how to optimize your design.
Highlight feedback loops that are inhibiting optimizations.
Flatten subsystem hierarchy to enable more extensive area and speed optimization.
Optimization with constrained overclocking and how it works.
Insert matching delays along all data paths.
The generated model is an intermediate model that shows the HDL implementation architecture and includes latency.
Improve readability of generated HDL code and optimize area usage.
Optimize unused ports in generated HDL code in combination with redundant logic deletion.
Area and timing optimizations that simplify constants and optimize mathematical operations.
Generate enable-based constraints for synthesis tools to meet timing requirements of multicycle paths in single clock mode.
Learn how to resolve numerical mismatch issues after HDL code generation.