Real Reciprocal HDL Optimized

R2026b

Compute reciprocal and generate optimized HDL code

• 

Real Reciprocal HDL Optimized block

To add a block to a model, double-click the canvas and start typing the block name. Then, select the block from the list.

Libraries:
Fixed-Point Designer HDL Support / Math Operations

Description

The Real Reciprocal HDL Optimized block computes 1/u, where u is a real-valued input.

Limitations

Data type override is not supported for the Real Reciprocal HDL Optimized block.

Ports

Input

u — Value to take reciprocal of

scalar | vector | matrix

Value to take the reciprocal of, specified as a real-valued scalar, vector, or matrix.

Slope-bias representation is not supported for fixed-point data types.

Data Types: single | double | fixed point

validIn — Whether input is valid

boolean scalar

Whether input is valid, specified as a Boolean scalar. This control signal indicates when the data from the u input port is valid. When this value is 1 (true), the block captures the value at the u input port. When this value is 0 (false), the block ignores the input samples.

Data Types: Boolean

Output

y — Reciprocal

scalar | vector | matrix

Reciprocal, returned as a real scalar, vector, or matrix of the same dimension as input u and with the data type specified by the Output datatype parameter.

Data Types: single | double | fixed point

divideByZero — Whether value at output port is result of division by zero

boolean scalar | vector | matrix

Since R2024b

Whether the value at the y output port is the result of a division by zero operation, returned as a Boolean scalar, vector, or matrix of the same dimension as input u. When the value of this signal is 1 (true), the corresponding output value at the y port is the result of division by zero. When the value of this signal is 0 (false), the corresponding output value at the y port is the result of division by a nonzero value.

See Division by Zero Behavior for a description of the default divide by zero behavior.

Dependencies

To enable this port, select the Show divide by zero port parameter.

Data Types: Boolean

validOut — Whether output data is valid

boolean scalar

Whether output data is valid, returned as a Boolean scalar. When the value of this control signal is 1 (true), the block has successfully computed the output at port y. When this value is 0 (false), the output data is not valid.

Data Types: Boolean

Parameters

To edit block parameters interactively, use the Property Inspector. From the Simulink^® Toolstrip, on the Simulation tab, in the Prepare gallery, select Property Inspector.

Main

Approximation method — Algorithm to use for approximation of reciprocal

CORDIC (default) | Lookup Table

Since R2026b

Algorithm to use for approximation of reciprocal, specified as CORDIC or Lookup Table. For more information, see CORDIC Versus Lookup Table Approximation Methods.

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

To get the block parameter value programmatically, use the get_param function.

Parameter:	ApproximationMethod
Values:	CORDIC (default) | Lookup Table
Data Types:	char | string

Example: set_param(gcb,"ApproximationMethod","CORDIC")

Output datatype — Data type of output

fixdt(1,18,10) (default) | single | double | fixdt(1,16,0) | <data type expression>

Data type of output at port y, specified as fixdt(1,18,10), single, double, fixdt(1,16,0), or a user-specified data type expression. The type can be specified directly or expressed as a data type object, such as Simulink.NumericType.

In R2024b: Unsigned data types are supported for this parameter.

Tips

• Click the Show data type assistant button to open the Data Type Assistant, an interactive graphical tool that simplifies the task of specifying the data type for this block. For more information, see Specify Data Types Using Data Type Assistant.

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

To get the block parameter value programmatically, use the get_param function.

Parameter:	OutputType
Values:	fixdt(1,18,10) (default) | single | double | fixdt(1,16,0) | <data type expression>
Data Types:	char | string

Example: set_param(gcb,"OutputType","fixdt(1,16,0)")

Show divide by zero port — Whether to show divideByZero port

off (default) | on

Since R2024b

Select this parameter to show the divideByZero port.

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

To get the block parameter value programmatically, use the get_param function.

Parameter:	dbzPort
Values:	0 (false) (default) | 1 (true)
Data Types:	logical

Example: set_param(gcb,"dbzPort",1)

Pipeline Configurations

Pipeline configuration parameters are enabled when the Approximation method parameter is set to CORDIC.

Automatically select CORDIC maximum shift value based on input word length — Option to automatically select CORDIC maximum shift value based on input word length

on (default) | off

Since R2024b

Option to automatically select the CORDIC maximum shift value based on input word length. When this parameter is selected, the default CORDIC maximumShiftValue is equal to wl - 1, where wl = u.WordLength + ~issigned(u).

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

To get the block parameter value programmatically, use the get_param function.

Parameter:	autoMaximumShiftVal
Values:	on (default) | off
Data Types:	char | string

Example: set_param(gcb,"autoMaximumShiftVal","off")

CORDIC maximum shift value — Maximum shift value of linear vectoring CORDIC

wl - 1 (default) | 10 | positive integer-valued scalar

Since R2024b

Maximum shift value of linear vectoring CORDIC, specified as a positive integer-valued scalar. The default value for this parameter is wl - 1, where wl = u.WordLength + ~issigned(u).

Dependencies

To enable this parameter, clear the Automatically select CORDIC maximum shift value based on input word length parameter.

Tips

See How to Interface with the Real Reciprocal HDL Optimized Block for more information.

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

To get the block parameter value programmatically, use the get_param function.

Parameter:	maximumShiftValue
Values:	10 (default) | positive integer-valued scalar
Data Types:	char | string

Example: set_param(gcb,"maximumShiftValue","10")

Number of iterations per pipeline register — Number of CORDIC iterations to perform per pipeline stage

1 (default) | positive integer-valued scalar

Since R2024b

Number of CORDIC iterations to perform per pipeline stage, specified as a positive integer-valued scalar.

For more information on how this parameter impacts latency and hardware resource utilization, see How to Interface with the Real Reciprocal HDL Optimized Block, Latency, and Effect of nIterPerReg on Latency and Hardware Resource Utilization. Use the Data Type Agent for Reciprocal HDL Optimized Blocks to generate an interactive visualization showing the effects of this parameter on pipelining allocation and latency.

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

To get the block parameter value programmatically, use the get_param function.

Parameter:	nIterPerReg
Values:	1 (default) | positive integer-valued scalar
Data Types:	char | string

Example: set_param(gcb,"nIterPerReg","2")

Tips

• The behavior of the Real Reciprocal HDL Optimized block with Approximation method set to CORDIC is equivalent to the fixed.cordicReciprocal function. When the input to the function is a real number with a binary-point scaled fixed-point data type, the function and block provide bit-exact results.

• The behavior of the Real Reciprocal HDL Optimized block with Approximation method set to Lookup Table is equivalent to the embblk.lookupTableReciprocal function. When the input to the function is a real number with a binary-point scaled fixed-point data type, the function and block provide bit-exact results.

Algorithms

CORDIC Versus Lookup Table Approximation Methods

Overview

When the Approximation method parameter is set to CORDIC, the block implements a counting leading zeros (CLZ) based normalizer and a linear vectoring CORDIC reciprocal kernel. The numeric and hardware performance are determined by the data types and the configuration of the CORDIC algorithm. For more information, see How to Set CORDIC Input Word Length and Maximum Shift Value to Achieve Desired Precision.

When the Approximation method parameter is set to Lookup Table, the block implements a counting leading zeros (CLZ) based normalizer and a lookup table approximation of the division operation with linear interpolation between breakpoints. The lookup table size is less than or equal to 36 Kb. If the input word length is less than 12 bits, the block implements a direct lookup table without interpolation.

To choose between the CORDIC and Lookup Table approximation methods, consider your requirements for Precision, Latency, clock rate, and hardware resource utilization. At a high level, when the precision and clock rate requirements are met, the lookup table approximation method usually requires fewer hardware resources and has a smaller latency. The CORDIC approximation method can achieve high precision with large data types at the cost of increased latency and hardware resources. The CORDIC algorithm uses only shift-add operations, resulting in a higher clock rate. The precision of the lookup table approximation method has a maximum relative error of 2^-21, even with rich data types. The precision of both approximation methods is also limited by the range of the input and the precision of the output data type due to the nature of the reciprocal operation. For a direct comparison on hardware for various input data types, see Hardware Resource Utilization and Performance of CORDIC and Lookup Table Approximation Methods.

Precision

The precision of the approximation method is defined as the estimated relative error upper bound.

The precision of the CORDIC approximation method is determined by the input data type, while the precision of the lookup table approximation is bounded to a maximum relative error of 2^-21. If less precision is required, the lookup table approximation is usually more efficient on hardware. If high precision (maximum relative error < 2^-21) is required, use the CORDIC approximation method.

The precision of both the CORDIC and lookup table approximation methods are limited by the input integer length and the output fraction length, due to the nature of the reciprocal operation. A larger input results in a smaller output, such that more input integer bits require more output fraction bits.

Approximation Method	Estimated Relative Error Upper Bound
CORDIC	log2(Erelative) <= max(-n+1,-wl+log2(n)+1,-fout+iin), where: n = maximumShiftValue wl = u.WordLength + ~issigned(u) fout = OutputType fraction length iin = input type integer length
Lookup Table	log2(Erelative) <= max(-21,-fout+iin+1), where: fout = OutputType fraction length iin = input type integer length

Latency

The latency of the Real Reciprocal HDL Optimized block is defined from the input to the corresponding output. For example, as shown in How to Interface with the Real Reciprocal HDL Optimized Block, from In1 to Out1, In2 to Out2, and In3 to Out3.

The latency of the block using the CORDIC approximation method depends on the input data type.

Input Type	Latency of CORDIC Approximation
Fixed point or scaled double fi	ceil((nextpow2(u.WordLength) + maximumShiftValue)/nIterPerReg) + 1, where wl = u.WordLength + ~issigned(u) and maximumShiftValue = wl - 1 or user-specified value.
Floating point	0

The latency of the block using the lookup table approximation method depends on the input data type.

Input Type	Latency of Lookup Table Approximation
Fixed point or scaled double fi	(u.WordLength > 11)*3 + issigned(u)*2 + 5 + max(nextpow2(u.WordLength) - 3,0)
Floating point	0

For quick reference, this table provides latency of the block using the lookup table approximation for a given input word length and signedness.

Input Word Length	Latency of Lookup Table Approximation Unsigned Input	Latency of Lookup Table Approximation Signed Input
<= 8 bits	5	7
9 ~ 11 bits	6	8
>= 12 bits	nextpow2(u.WordLength) + 5	nextpow2(u.WordLength) + 7

Hardware Resource Utilization and Performance of CORDIC and Lookup Table Approximation Methods

This block supports HDL code generation using the Simulink HDL Workflow Advisor. For examples, see HDL Code Generation and FPGA Synthesis from Simulink Model (HDL Coder) and Implement Digital Downconverter for FPGA (DSP HDL Toolbox).

This example data was generated by synthesizing the block on an AMD^® Zynq^® ZC706 evaluation kit. The synthesis tool was Vivado^® v2025.1.1.

These synthesis results compare the CORDIC approximation method to the Lookup Table approximation method in terms of precision, clock rate, latency, and hardware resource utilization for a selection of input data types.

For this synthesis, the input was scalar. For the CORDIC approximation method, default parameter values were used.

Approximation Method	Input Data Type	Output Data Type	log2(Erelative)	Clock Frequency (MHz)	Latency	Slice LUTs Usage	Slice Registers Usage	DSP Usage	Block RAM Tile Usage
CORDIC	sfix8_en4	sfix64_en32	-4.1926	786.58	11	259	145	0	0
Lookup Table	sfix8_en4	sfix64_en32	-21	437.19	7	179	140	0	0.5
CORDIC	sfix16_en8	sfix64_en32	-11.0931	720.98	20	679	545	0	0
Lookup Table	sfix16_en8	sfix64_en32	-21	437.19	11337		254	1	1
CORDIC	sfix32_en16	sfix64_en40	-25	550.36	37	2040	2122	0	0
Lookup Table	sfix32_en16	sfix64_en40	-21	428.39	12	557	407	1	1

How to Interface with the Real Reciprocal HDL Optimized Block

Because of its fully pipelined nature, the Real Reciprocal HDL Optimized block is able to accept input data on any cycle, including consecutive clock cycles. To send input data to the block, the validIn signal must be true. When the block has finished the computation and is ready to send the output, it changes validOut to true for one clock cycle. For inputs set of consecutive cycles, validOut is also set to true.

When the Approximation method parameter is set to CORDIC, the block uses fully pipelined architecture that implements a counting leading zeros (CLZ) based normalizer and a linear vectoring CORDIC reciprocal kernel. If the input u is a fixed-point or scaled double data type, the block uses multiple pipeline stages for computation. If the input is a signed data type, the normalization requires nextpow2(u.WordLength) iterations. The number of CORDIC iterations depends on the value of the CORDIC maximum shift value parameter. A larger word length can provide higher resolution, but requires more iterations to process. The Real Reciprocal HDL Optimized block can perform multiple iterations per pipeline stage, which results in lower latency at the cost of a longer critical path in the generated HDL code.

For example, if the word length of the input u is 18, then normalization requires 5 iterations. If the Automatically select CORDIC maximum shift value based on input word length parameter is selected, the CORDIC maximum shift value is 18 - 1 = 17 and requires 17 iterations. The total number of iterations is 5 + 17 = 22 and the latency of the block is ceil((total number of iterations)/nIterPerReg) + 1. If the number of iterations per pipeline register is set to 1, then the block latency is 23; if the number of iterations per pipeline register is set to 2, then the block latency is 12. If the number of iterations per pipeline register is greater than the total number of required iterations, the block performs all iterations in one pipeline stage and the total latency is minimized to 2.

Effect of nIterPerReg on Latency and Hardware Resource Utilization

This block supports HDL code generation using the Simulink HDL Workflow Advisor. For examples, see HDL Code Generation and FPGA Synthesis from Simulink Model (HDL Coder) and Implement Digital Downconverter for FPGA (DSP HDL Toolbox).

This example data was generated by synthesizing the block on a Xilinx^® Zynq-7000 xc7z045 SoC. The synthesis tool was Vivado v2023.1.2.

These synthesis results show the effect of the Number of iterations per pipeline register parameter on the latency and hardware resource utilization.

nIterPerReg = 1

These parameters were used for synthesis:

• Input data type — sfix18_en10

• Output data type — sfix18_en10

• Input dimension — scalar

• Automatically select CORDIC maximum shift value based on input word length — on

• Number of iterations per pipeline register — 1

• Target frequency — 500 MHz

• Latency for this configuration — 23

Resource	Usage	Available	Utilization (%)
Slice LUTs	815	218600	0.37
Slice Registers	703	437200	0.16
DSPs	0	900	0.00
Block RAM Tile	0	545	0.00
URAM	0	0

	Value
Requirement	2 ns (500 MHz)
Data Path Delay	1.74 ns
Slack	0.176 ns
Clock Frequency	548.25 MHz

nIterPerReg = 2

These parameters were used for synthesis:

• Input data type — sfix18_en10

• Output data type — sfix18_en10

• Input dimension — scalar

• Automatically select CORDIC maximum shift value based on input word length — on

• Number of iterations per pipeline register — 2

• Target frequency — 300 MHz

• Latency for this configuration — 12

Resource	Usage	Available	Utilization (%)
Slice LUTs	705	218600	0.32
Slice Registers	374	437200	0.09
DSPs	0	900	0.00
Block RAM Tile	0	545	0.00
URAM	0	0

	Value
Requirement	3.3333 ns (300 MHz)
Data Path Delay	2.65 ns
Slack	0.676 ns
Clock Frequency	376.32 MHz

nIterPerReg = 3

These parameters were used for synthesis:

• Input data type — sfix18_en10

• Output data type — sfix18_en10

• Input dimension — scalar

• Automatically select CORDIC maximum shift value based on input word length — on

• Number of iterations per pipeline register — 3

• Target frequency — 200 MHz

• Latency for this configuration — 9

Resource	Usage	Available	Utilization (%)
Slice LUTs	680	218600	0.31
Slice Registers	281	437200	0.06
DSPs	0	900	0.00
Block RAM Tile	0	545	0.00
URAM	0	0

	Value
Requirement	5 ns (200 MHz)
Data Path Delay	3.889 ns
Slack	1.125 ns
Clock Frequency	258.06 MHz

Division by Zero Behavior

When the input u is 0 and has a fixed-point data type, then the output y is equal to upperbound(Output datatype).

For floating-point inputs, the Real Reciprocal HDL Optimized block follows IEEE^® Standard 754.

References

[1] Volder, Jack E. “The CORDIC Trigonometric Computing Technique.” IRE Transactions on Electronic Computers EC-8, no. 3 (Sept. 1959): 330–34.

[2] Andraka, Ray. “A Survey of CORDIC Algorithm for FPGA Based Computers.” In Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 191–200. https://dl.acm.org/doi/10.1145/275107.275139.

[3] Walther, J.S. “A Unified Algorithm for Elementary Functions.” In Proceedings of the May 18-20, 1971 Spring Joint Computer Conference, 379–86. https://dl.acm.org/doi/10.1145/1478786.1478840.

[4] Schelin, Charles W. “Calculator Function Approximation.” The American Mathematical Monthly, no. 5 (May 1983): 317–25. https://doi.org/10.2307/2975781.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

Slope-bias representation is not supported for fixed-point data types.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays in the design. Distributed pipelining does not redistribute these registers. The default value is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
In R2024b: FlattenHierarchy	Removes Real Reciprocal HDL Optimized block hierarchy from generated HDL code. The default is inherit. See also FlattenHierarchy (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see OutputPipeline (HDL Coder).

Restrictions

Supports fixed-point data types only.

Version History

Introduced in R2021a

R2026b: Real Reciprocal HDL Optimized Block: New lookup table approximation method

The Real Reciprocal HDL Optimized block now includes a lookup table approximation method in addition to the existing CORDIC approximation method. This choice of approximation method allows you better adjust the block to meet your requirements for precision, latency, clock rate, and hardware resource utilization.

The new embblk.lookupTableReciprocal function is equivalent to the Real Reciprocal HDL Optimized block using the lookup table approximation.

R2024b: Custom pipelining, improved latency and resource utilization, optional divide by zero port

Several improvements have been made to the Real Reciprocal HDL Optimized block:

• Custom pipelining is supported via the new CORDIC maximum shift value and Number of iterations per pipeline register parameters.

• The latency of this block has been reduced. Latency depends on the specified data type and pipeline configuration. See How to Interface with the Real Reciprocal HDL Optimized Block for more information.

• HDL resource utilization has been further optimized to require fewer hardware resources. See Effect of nIterPerReg on Latency and Hardware Resource Utilization for example synthesis results.

• An optional divideByZero port has been added to output a flag when the corresponding output is a result of division by zero.

R2024b: Support for unsigned output

The Real Reciprocal HDL Optimized block now supports unsigned data types for the Output datatype parameter.