bitsrl

Bit shift right logical

Syntax

c = bitsrl(a, k)

Description

c = bitsrl(a, k) returns the result of a logical right shift by k bits on input a for fixed-point operations. bitsrl shifts zeros into the positions of bits that it shifts right. It does not check overflow or underflow.

bitsrl ignores fimath properties such as RoundingMode and OverflowAction.

When a is a fi object, a and c have the same associated fimath and numerictype objects.

Examples

Shift Right a Signed fi Input

Shift a signed fi input right by 1 bit.

Create a signed fixed-point fi object with a value of -8, word length 4, and fraction length 0 and display its binary value.

a = fi(-8,1,4,0);
disp(bin(a))

1000

Shift a right by 1 bit, and display the binary value.

disp(bin(bitsrl(a,1)))

0100

bitsrl shifts a zero into the position of the bit that it shifts right.

Shift Right Using a fi Shift Value

Shift right a built-in int8 input using a fi shift value.

k = fi(2);
a = int8(64);
bitsrl(a,k)

ans = int8

16

Shift Right a Built-in uint8 Input

Use bitsrl to shift a uint8 input right by 2 bits.

a = uint8(64);
bitsrl(a,2)

ans = uint8

16

Input Arguments

a — Data that you want to shift

scalar | vector | matrix | multidimensional array

Data that you want to shift, specified as a scalar, vector, matrix, or multidimensional array.

Data Types: fi | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64

Complex Number Support: Yes

k — Number of bits to shift

non-negative integer-valued scalar

Number of bits to shift, specified as a non-negative integer-valued scalar.

Data Types: fi|single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using MATLAB® Coder™.

Usage notes and limitations:

• Generated code might not handle out of range shifting.

GPU Code Generation

Generate CUDA® code for NVIDIA® GPUs using GPU Coder™.

Usage notes and limitations:

• Generated code might not handle out of range shifting.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Generates srl operator in VHDL^®.

Generates >> operator in Verilog^®.

Version History

Introduced in R2007b