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setModuleProperty

Class: dlhdl.ProcessorConfig
Package: dlhdl

Use the setModuleProperty method to set properties of modules within the dlhdl.ProcessorConfig object

Syntax

setModuleProperty(ModuleName,Name,Value)

Description

The setModuleProperty(ModuleName,Name,Value)method sets the properties of the module mentioned in ModuleName by using the values specified as Name,Value pairs.

Input Arguments

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The dlhdl.ProcessorConfig object module name, specified as a character vector or string.

Name-Value Arguments

Specify optional comma-separated pairs of Name,Value arguments. Name is the argument name and Value is the corresponding value. Name must appear inside quotes. You can specify several name and value pair arguments in any order as Name1,Value1,...,NameN,ValueN.

Example:
conv module parameters

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Use this parameter to control generation of the convolution module as a part of the deep learning processor configuration.

Example: 'ModuleGeneration', 'on'

Use this parameter to control generation of the LRN block as a part of the convolution module of the deep learning processor configuration.

Example: 'LRNBlockGeneration', 'on'

This parameter is the number of parallel 3-by-3 convolution kernel threads that are a part of the conv module within the dlhdl.ProcessorConfig object.

Example: 'ConvThreadNumber', 64

This parameter is a 3D matrix representing input image size limited by the conv module BRAM size within the dlhdl.ProcessorConfig object.

Example: 'InputMemorySize', [227 227 3]

This parameter is a 3D matrix representing output image size limited by the conv module BRAM size within the dlhdl.ProcessorConfig object.

Example: 'OutputMemorySize', [227 227 3]

This parameter is a positive integer representing the maximum input and output feature size as a part of the conv module within the dlhdl.ProcessorConfig object.

Example: 'FeatureSizeLimit', 512

fc module parameters

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Use this parameter to control generation of the fully connected module as a part of the deep learning processor configuration.

Example: 'ModuleGeneration', 'on'

Use this parameter to control generation of the Softmax block as a part of the fully connected module of the deep learning processor configuration. When you set this property to off, the Softmax layer is still implemented in software.

Example: 'SoftmaxBlockGeneration', 'on'

This parameter is the number of parallel fc MAC threads that are a part of the fc module within the dlhdl.ProcessorConfig object.

Example: 'FCThreadNumber', 16

This parameter is an unsigned integer representing cache BRAM size limited by the fc module BRAM size within the dlhdl.ProcessorConfig object.

Example: 'InputMemorySize', 9216

This parameter is an unsigned integer representing cache BRAM size limited by the fc module BRAM size within the dlhdl.ProcessorConfig object.

Example: 'OutputMemorySize', 4096

adder module properties

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Use this parameter to control generation of the adder module as a part of the deep learning processor configuration.

Example: 'ModuleGeneration', 'on'

This parameter is an unsigned integer representing cache BRAM size limited by the adder module BRAM size within the dlhdl.ProcessorConfig object.

Example: 'InputMemorySize', 40

This parameter is an unsigned integer representing cache BRAM size limited by the adder module BRAM size within the dlhdl.ProcessorConfig object.

Example: 'OutputMemorySize', 40

Examples

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  1. Create an example object by using the dlhdl.ProcessorConfig class, and then use the setModuleProperty method to set the value for convThreadNumber.

    hPC = dlhdl.ProcessorConfig;
    hPC.setModuleProperty("conv","ConvThreadNumber",25)
    hPC
  2. Once you execute the code, the result is:

    hPC = 
    
                        Processing Module "conv"
                                ModuleGeneration: 'on'
                              LRNBlockGeneration: 'on'
                     SegmentationBlockGeneration: 'on'
                                ConvThreadNumber: 25
                                 InputMemorySize: [227 227 3]
                                OutputMemorySize: [227 227 3]
                                FeatureSizeLimit: 2048
    
                          Processing Module "fc"
                                ModuleGeneration: 'on'
                          SoftmaxBlockGeneration: 'off'
                                  FCThreadNumber: 4
                                 InputMemorySize: 25088
                                OutputMemorySize: 4096
    
                       Processing Module "adder"
                                ModuleGeneration: 'on'
                                 InputMemorySize: 40
                                OutputMemorySize: 40
    
                  Processor Top Level Properties
                                  RunTimeControl: 'register'
                              InputDataInterface: 'External Memory'
                             OutputDataInterface: 'External Memory'
                               ProcessorDataType: 'single'
    
                         System Level Properties
                                  TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                                 TargetFrequency: 200
                                   SynthesisTool: 'Xilinx Vivado'
                                 ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                         SynthesisToolChipFamily: 'Zynq UltraScale+'
                         SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                        SynthesisToolPackageName: ''
                         SynthesisToolSpeedValue: ''
    
    
  1. Create an example object by using the dlhdl.ProcessorConfig class, and then use the setModuleProperty method to set the value for InputMemorySize.

    hPC = dlhdl.ProcessorConfig;
    hPC.setModuleProperty("fc","InputMemorySize",25060)
    hPC
  2. Once you execute the code, the result is:

    hPC = 
    
                        Processing Module "conv"
                                ModuleGeneration: 'on'
                              LRNBlockGeneration: 'on'
                     SegmentationBlockGeneration: 'on'
                                ConvThreadNumber: 16
                                 InputMemorySize: [227 227 3]
                                OutputMemorySize: [227 227 3]
                                FeatureSizeLimit: 2048
    
                          Processing Module "fc"
                                ModuleGeneration: 'on'
                          SoftmaxBlockGeneration: 'off'
                                  FCThreadNumber: 4
                                 InputMemorySize: 25060
                                OutputMemorySize: 4096
    
                       Processing Module "adder"
                                ModuleGeneration: 'on'
                                 InputMemorySize: 40
                                OutputMemorySize: 40
    
                  Processor Top Level Properties
                                  RunTimeControl: 'register'
                              InputDataInterface: 'External Memory'
                             OutputDataInterface: 'External Memory'
                               ProcessorDataType: 'single'
    
                         System Level Properties
                                  TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                                 TargetFrequency: 200
                                   SynthesisTool: 'Xilinx Vivado'
                                 ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                         SynthesisToolChipFamily: 'Zynq UltraScale+'
                         SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                        SynthesisToolPackageName: ''
                         SynthesisToolSpeedValue: ''
    
    
  1. Create an example object by using the dlhdl.ProcessorConfig class, and then use the setModuleProperty method to set the value for InputMemorySize.

    hPC = dlhdl.ProcessorConfig;
    hPC.setModuleProperty("adder","InputMemorySize",80)
    hPC
  2. Once you execute the code, the result is:

    hPC = 
    
                        Processing Module "conv"
                                ModuleGeneration: 'on'
                              LRNBlockGeneration: 'on'
                     SegmentationBlockGeneration: 'on'
                                ConvThreadNumber: 16
                                 InputMemorySize: [227 227 3]
                                OutputMemorySize: [227 227 3]
                                FeatureSizeLimit: 2048
    
                          Processing Module "fc"
                                ModuleGeneration: 'on'
                          SoftmaxBlockGeneration: 'off'
                                  FCThreadNumber: 4
                                 InputMemorySize: 25088
                                OutputMemorySize: 4096
    
                       Processing Module "adder"
                                ModuleGeneration: 'on'
                                 InputMemorySize: 80
                                OutputMemorySize: 40
    
                  Processor Top Level Properties
                                  RunTimeControl: 'register'
                              InputDataInterface: 'External Memory'
                             OutputDataInterface: 'External Memory'
                               ProcessorDataType: 'single'
    
                         System Level Properties
                                  TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                                 TargetFrequency: 200
                                   SynthesisTool: 'Xilinx Vivado'
                                 ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                         SynthesisToolChipFamily: 'Zynq UltraScale+'
                         SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                        SynthesisToolPackageName: ''
                         SynthesisToolSpeedValue: ''
    
    
  1. Create an example object by using the dlhdl.ProcessorConfig class, and then use the setModuleProperty method to set the value for ModuleGeneration.

    hPC = dlhdl.ProcessorConfig;
    hPC.setModuleProperty("conv","ModuleGeneration", "off")
    hPC
  2. Once you execute the code, the result is:

    hPC = 
    
                        Processing Module "conv"
                                ModuleGeneration: 'off'
    
                          Processing Module "fc"
                                ModuleGeneration: 'on'
                          SoftmaxBlockGeneration: 'off'
                                  FCThreadNumber: 4
                                 InputMemorySize: 25088
                                OutputMemorySize: 4096
    
                       Processing Module "adder"
                                ModuleGeneration: 'on'
                                 InputMemorySize: 40
                                OutputMemorySize: 40
    
                  Processor Top Level Properties
                                  RunTimeControl: 'register'
                              InputDataInterface: 'External Memory'
                             OutputDataInterface: 'External Memory'
                               ProcessorDataType: 'single'
    
                         System Level Properties
                                  TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                                 TargetFrequency: 200
                                   SynthesisTool: 'Xilinx Vivado'
                                 ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                         SynthesisToolChipFamily: 'Zynq UltraScale+'
                         SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                        SynthesisToolPackageName: ''
                         SynthesisToolSpeedValue: ''
    
    
Introduced in R2020b