Main Content

dlhdl.buildProcessor

Build and generate custom processor IP

    Description

    example

    dlhdl.buildProcessor generates a bitstream for the default dlhdl.ProcessorConfig object.

    dlhdl.buildProcessor(processorconfigobject)generates a bitstream for the processorconfigobject object.

    dlhdl.buildProcessor(processorconfigobject,Name,Value) generates a bitstream for the processorconfigobject object, with additional options specified by one or more Name,Value arguments.

    Examples

    Generate Custom Bitstream for Custom Processor Configuration

    Create a custom processor configuration. Generate a bistream for the custom processor configuration.

    Create a dlhdl.ProcessorConfig object. Save the object in hPC.

    hPC = dlhdl.ProcessorConfig

    Generate a custom bitstream for hPC

    dlhdl.buildProcessor(hPC)

    Generate Custom Bitstream and Specify Project Folder Name, Deep Learning Processor IP Core Name, and Target Code Generation language

    Create a custom deep learning processor configuration. When you generate code specify the project folder name, deep learning processor IP core name, and target code generation language.

    hPC = dlhdl.ProcessorConfig;
    dlhdl.buildProcessor(hPC,'ProjectFolder','fconlyprocessor_prj',...
    'ProcessorName','fconlyprocessor','HDLCoderConfig',{'TargetLanguage','Verilog'});

    Input Arguments

    collapse all

    Name of the custom processor configuration object, specified as a variable of type dlhdl.Processorconfig.

    Example: dlhdl.buildProcessor(hPC)

    Name-Value Arguments

    Specify optional comma-separated pairs of Name,Value arguments. Name is the argument name and Value is the corresponding value. Name must appear inside quotes. You can specify several name and value pair arguments in any order as Name1,Value1,...,NameN,ValueN.

    Example:

    Name of project folder where generated files are saved

    Example: 'ProjectFolder', 'fconlyprocessor_prj'

    Name of generated deep learning processor IP core

    Example: 'ProcessorName', 'fconlyprocessor'

    Specify whether to generate VHDL or Verilog code.

    Example: 'HDLCoderConfig',{'TargetLanguage','Verilog'}

    Introduced in R2020b