Program the Design onto an FPGA Using Vivado | Getting Started with the Avnet ZUBoard, Part 4 - MATLAB & Simulink
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    Program the Design onto an FPGA Using Vivado | Getting Started with the Avnet ZUBoard, Part 4

    From the series: Getting Started with the Avnet ZUBoard

    Synthesize, implement, and program a FIR filter onto the Avnet® ZUBoard hardware using AMD-Xilinx® Vivado® Design Suite. Target a specific FPGA device and perform place-and-route. Specify how input and output signals are assigned to package pins. Rerun the simulation and make sure performance meets design guidelines. Lastly, create a final bitstream file and program the FIR filter onto ZUBoard hardware.

    Published: 26 Aug 2022

    Hello there. How would you like to learn how to program the Avnet ZUBoard development kit using AMD-Xilinx Vivado?

    I'm John Pitrus with MathWorks. This is the four-part video series that covers getting started with the Avnet ZUBoard development kit. During the first three videos, I showed you how to set up the project, design an algorithm and simulate it, elaborate the design. And today's focus is going to be creating a bitstream file and programming the FPGA hardware.

    During the last video, we ran a behavioral simulation, and that came back without errors. So let's look at what Vivado did to our design.

    Vivado has created a set of files known as the elaborated design. And what this means is it took our FIR filter and placed it into specific function blocks, netlists, and IOs within the Vivado environment. And here's what it looks like. So you get a project summary and a picture of the schematic. What you'll want to do next is run synthesis, which I'll do here.

    And it looks like synthesis ran successfully. So let's go ahead and open that.

    Synthesis is really an estimation and a design-planning step. When I placed IOs, I right-clicked here and just had Vivado auto-place everything. And you can see on the left here, you get a lot of different views on timing, debugging, clock interaction, design-rule check, noise reporting, and utilization, to see how your design performs given this set of synthesis files.

    So when we look at how IOs were mapped to the package and what the final silicon die and device looks like, this seems OK. So we'll go ahead to the next step, which is running the implementation.

    And it looks like implementation worked successfully.

    Implementation is done. Vivado has created a set of files that now represent our FIR filter design, placed on the FPGA device all of the functions in the blocks around the device die, and all of the IO are mapped to physical pins of the package.

    So the last step we'll want to do is generate a bitstream. Let's move that to a split-screen view.

    And you can see the bitstream generated successful. And you can use that file to program your board.

    So let's review what we've covered. In today's video, I showed you how to create a bitstream and program the FPGA as part of the ZUBoard development kit. Thanks for watching, and good luck on your next design.

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