ASIC and FPGA Workflow for ISO 26262 and IEC 61508

Beginning with Release 2020a, HDL Coder has been qualified for ISO 26262, including ASIL D. IEC Certification Kit for ISO 26262 and IEC 61508 from MathWorks has been updated with a full workflow for connecting Model-Based Design to FPGA and ASIC implementation.

The kit provides workflows and artifacts to help you comply with – and prove that you comply with – these functional safety standards. Under the HDL section, there’s a certificate from TÜV SÜD for HDL Coder, along with their report explaining the process used to qualify it.

And this is more than just HDL Coder. The workflow document in the kit covers the process from requirements authoring, to architectural modeling, to modeling for implementation, then to HDL code generation, with verification and validation at each step.

As you can see, a big part of this workflow is first verifying that the model behaves according to requirements, which includes linking requirements to the models and tests, and making sure those requirements are fully covered in testing. Then as you get into implementation, verifying that each implementation stage produces a design whose functionality matches that of the previous stage.

This workflow also provides techniques to help ensure integrity through downstream FPGA or ASIC implementation. Before HDL code generation, use the Model Advisor to run task-specific checks. Here I will just run the ISO checks on our HDL tutorial design, which is a signal processing design that was not created with certification in mind, so it should identify plenty of issues.

There are no errors, which is good, and the warnings can give you an idea of good practices to prevent assumptions at this level, causing issues downstream. Some of these should be addressed in the design, and some involve tool settings such as increasing the severity of checks for issues such as overflow.

And in terms of verifying the downstream implementation, HDL Verifier offers a number of ways to re-use your Model-Based Design work. What’s shown in this flow diagram is running your design on an FPGA running in-the-loop with your Simulink tests, and checking the results back-to-back against your model. You can also use HDL Verifier to generate SystemVerilog verification components for downstream simulation, including UVM. See the HDL Verifier product page to learn more.

This kit also shows how to integrate handwritten code into the process, and how to verify it together with your model using HDL Verifier.

Finally, the kit provides a template you can use for your project to demonstrate conformance. It lists the criteria used and prompts you for the relevant information used in your process.

MathWorks offers assistance and consulting to build your organizational proficiency with these functional safety workflows. And the kit itself provides some great resources to get you started.