Answered
Kalman filter for FPGA in HDL Coder?
You need to break the MATLAB code into design and testbench and use MATLAB to HDL code advisor. See the sample example below. ...

2 years ago | 0

| accepted

Answered
Unable to find an installed compiler.
If mex -setup points to a valid compiler; floating point to fixed point conversion should proceed without any errors. if this i...

2 years ago | 0

Answered
Is the creation of a test bench possible, without the use of the HDL coder software?
https://www.mathworks.com/products/matlab-test.html MATLAB Test provides tools for developing, executing, measuring, and managi...

2 years ago | 0

Answered
Do not undertand this error of missing license which contradicts 'license checkout statement'
... so that i can use it to generate HDL code for Microsemi Libero FPGA software ... You can try the examples in this page h...

2 years ago | 0

Answered
Please give latest version numbers of the following modules
Installing MATLAB and typing ver displays the latest version information https://www.mathworks.com/help/matlab/ref/ver.html ve...

2 years ago | 0

Answered
HDL user-defined block RAM
This usually implies generated HDL didn't meet the original MATLAB or Simulink results. Please reach out to technical support ...

2 years ago | 0

Answered
Is it possible to generate a VHDL File from a MATLAB Function that only contains one (clocked) process?
The current code style is driven by synthesis best practices. Please reach to technical support for additional customization r...

2 years ago | 0

Answered
HDL-Coder: initialization of internal VHDL-signals
All HDL Coder generated signals are fully initialized or driven with valid logic. Lack of valid drivers to signals is consid...

2 years ago | 0

Answered
How to create VHDL code of a Neural Network block created through GENSIM command ?
This example shows how to convert a neural network regression model (created using gensim) to HDL Code. https://www.mathworks...

2 years ago | 0

Answered
FPGA Synthesis and Analysis HDL coder
There are many reasons for the synthesis step to be taking a long time. If the generated HDL does not fit on the FPGA or very c...

2 years ago | 0

Answered
how can i use contiuous time integrator in hdl coder?
HDL Coder only generates code from discrete blocks. Continuous blocks are not supported. Consider using discrete time integrat...

2 years ago | 0

Answered
HDL work flow advisor for non evaluation board devices
https://www.mathworks.com/help/hdlcoder/create-a-custom-hardware-platform.html You can create your own custom reference desig...

2 years ago | 0

Answered
Compatibility of HDL coder with regression ensemble predict block and fixed point conversion
RegressionEnsemble Predict' block is currently not supported for HDL code generation. You need to build the block from first pr...

2 years ago | 0

Answered
Add 'MARK_DEBUG = "TRUE"' to signals in generated HDL
Currently synthesis attribute specification is limited to certain blocks like product block. This capability is planned for po...

2 years ago | 0

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Answered
Is it possible to generate parametrized HDL for Chart parameters?
https://www.mathworks.com/matlabcentral/answers/382489-how-are-generics-supported-in-hdl-coder Currently type generics are not ...

2 years ago | 0

Answered
The function of generating HDL code has an error with the names of blocks in the same Subsystem
" ... in the subsystem "OFDM Transmitter" will contain the subsystem "whdlOFDMTx Model". When I do generate HDL code, the name o...

2 years ago | 0

Answered
Why I get this error when working with hdl workflow?
This is an unexpected error. Can you reach out to customer support with reproduction steps? Thanks.

2 years ago | 1

Answered
Synthesize Matlab function with large input and output onto FPGA
You have a large IO design (in frames); the design needs conversion to samples. Prior to R2022b release there was no automation ...

2 years ago | 0

Answered
Can't generate Simulink model from Simulink function block
https://www.mathworks.com/help/hdlcoder/ug/hdl-optimizations-across-matlab-function-simulink-blocks.html You can convert a subs...

2 years ago | 0

Answered
How to read a matrix data from a subfunction by HDLs coder
https://www.mathworks.com/matlabcentral/fileexchange/50098-hdlcoder-design-patterns-and-examples HDLCoder Design Patterns and E...

2 years ago | 0

Answered
how to configure parameters for NCO(frequency shifting or frequency correction) simulink block set based on the NCO operation has performed in the matlab script
Please find attached a sample NCO block that can generate HDL code.

2 years ago | 0

| accepted

Answered
Deep Learning HDL Toolbox - Error using dnnfpga.compiler.codegenfpga Index exceeds the number of array elements. Index must not exceed 0.
This is not an expected error message. Please reach out to tech support for help and any available workaround.

2 years ago | 0

Answered
Error when converting design from Matlab Simulink to HDL
The model has an incorrect/undefined type specification. You need to use the fixdt(1,64,32) syntax. In addition, please n...

2 years ago | 0

Answered
HDL "complex to Magnitude and angle" module show critical path which can not meet 160MHz clock timing
Would you be able to share your model and HDL Coder code generation steps to reproduce the workflow?

2 years ago | 0

Answered
HDL Workflow Advisor - Step 3.2 - "Failed Index exceeds the number of array elements. Index must not exceed 2" in hdlturnkey.interface.ChannelBased/connectFrameInterfacePort
This is not an expected error message. Please reach out to tech support with reproduction steps.

2 years ago | 1

Answered
Converting Simulink Bus with mixed datatypes to an array of doubles
Can you share your current workaround? I wonder if this block would be of help in your usecase. Bus to Vector https://www.math...

2 years ago | 0

Answered
Simulink HDL Coder & Vitis Model Composer cannot find the same Device
Model Composer library in Simulink needs Vitis workflows to generate HDL Code. https://www.xilinx.com/products/design-tools/vit...

2 years ago | 0

Answered
How to initialize Dual rate Dual port ram?
RAM System object can be used as a block in Simulink and it supports Initial Value. The HDL library browser that ships with ...

2 years ago | 0

Answered
Why did I receive an error message：ISim engine error: Failed to Load up XSI.
Please try running with Vivado 2022.1. You can see our supported software in the documentation at: https://www.mathworks.com/hel...

2 years ago | 0

| accepted

Submitted

HDLCoder Design Patterns and Examples
Several tutorials in this submission show how to generate HDL from MATLAB code, Simulink models, and Simscape models.

2 years ago | 5 downloads |

4.7 / 5