GPS Receiver using Xilinx FPGA and TI DSP

These model files move from a system level GPS receiver channel to actual operating hardware.

This set of models elaborates a simple "system level" descrition of a GPS receiver channel all the way to operating hardware. Real world captured GPS signals are used to test the initial receiver design. Ultimatly, the design is elaborated to the point of being deployed on a Xilinx FPGA and TI DSP. NOTE: You do not have to have the tools to do this to use most of the models.