failed to receive a control packet from the FPGA target using Atlys Spartan 6

hello, I'm working with the example "Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop", I'm using Atlys Spartan 6 development board. I checked the connection via Ethernet with the FPGA, using ping command, and the verification tool in the FPGA in the loop wizard, and I found that it is working well. However, when I replace the controller and try to simulate the design, it gives me this error message: failed to receive a control packet from the FPGA target.