Using non-memory-mapped (NMM) ports with FPGA-in-the-loop (FIL) cosim with XUP Atlys Spartan 6 Dev Board

Hi,

I have a Digilent XUP Atlys Spartan 6 development board. FIL is supported with this board, however there does not seem to be any way to link (input from/output to) NMM ports (like I/O ports). Has anyone managed to use NMM ports with FIL? Is it possible? What I am really asking for I suppose is a type of workaround of the fact that the XUP Atlys board does not currently support ethernet-based hardware cosim; two examples of currently supported boards are the Spartan 3A 1800 DSP starter platform (the cheapest option by far at $595USD) and the ML402 Development board($1195USD).

The only other solution I can think of is to try and do(via other means described below), what Mathworks does automatically (via the FIL wizard and a bevy of p-files) for the supported boards; or at least try an get some similar functionality; i.e create my own communications server for the Atlys board to put it more succinctly. This would require using multiple Xilinx Sysgen Blackboxes say:

1. one for the TCP\IP Stack 2. another to decode the data and control information to input to 3. another blackbox which would be the actual device-under-test (DUT) (i.e. what I am actually designing and simulating). 4. another to encode data and control information to input back to simulink

On the Simulink side I would have to mux all the data and control information into packets and send via TCP/IP send and receive via TCP/IP Receive.

This is no trivial exercise(esp. since I have not even mentioned the synchronisation aspect of the undertaking), and would undoubtedly require much more than stated above; one can see why The Mathworks automated the process.

Any help or ideas would be greatly appreciated.

Thanks

Wil

Answer 1

[William Knox]

Hi All,

I found the solution. To manually create NMM ports perform the following steps; we will be creating a NMM port for the

1. Create a library folder for all your custom libraries for the atlys board.

2. Add this path to Matlab. File -> Set Path

3. Create a new library and save it to something meaningful like "atlys_nmm_ports_lib".

4. Copy a "Subsystem" block into the new library. Name the subsystem to something meaningful like "atlys_pmod0". Enter the subsystem by double clicking on it.

5. Copy the following blocks from Simulink into the subsystem(use library browser search function to find):

   A. "Out1" block (rename to something meaningful like PMOD0.
   B. "Convert" block (set to Boolean)
   C. "Gateway Out" block. (set name to pmod0).
   D. "Terminator".

6. Attach all these blocks together in the above order and save.

7. In the subsystem select the "Gateway Out" block (pmod0); click once only on the block to select it.

8. Go to the Matlab command window and type in the following:

>> xlSetNonMemMap(gcbh, 'Xilinx', 'ethernetcosim'); >> xlSetPortParams(gcbh, 'IOConstraint', 'NET "pmod0" LOC = T3;');

For information on these commands see the System Generator Reference Guide (sysgen_ref.pdf). Get(from Xilinx via Google or Internal Xilinx search), a version that equates to your version of system generator. Documentation on xlSetPortParams is non-existent except for a single website http://forums.xilinx.com/t5/DSP-Tools/How-to-build-non-memory-mapped-gateways/td-p/79261 from which this solution is derived. The initial aforementioned solution was provided by a Xilinx Employee. One may be able to use the documented function "xl_setparam(...)", but I haven't tried this.

9. To confirm the settings type:

>> dump(xlGetPortParams(gcbh))

10. Save.

11. Right click on the subsystem and select "Edit Mask". If "Edit Mask" option is not selectable, unlock the library -< "Edit" -> "Unlock Library".

12. Right-click on subsystem and select "Edit Mask".

13. I will provide the contents on my mask parameters but discussion of block masks is outside the scope of this solution. Ref: Google/Mathworks search on Block Masks.

Icon & Ports Tab

 patch([0 iWidth iWidth 0],[0 0 iHeight iHeight] , bg);
 patch(logoX,logoY, fg);
 plot([0 0 iWidth iWidth 0], [0 iHeight iHeight 0 0]);
 port_label(portdir,1,portstr);
 port_label('input',1,'PMOD0');
 text(iWidth-10,5,'nmm');

Parameters Tab

 #: 1
 Prompt: Provide Output Double
 Variable: show_out
 Type: checkbox
 Evaluate: {ticked}
 Tunable: {ticked}
 Tab name: {blank}

Icon & Ports Tab

 [bg,fg] = xlcmap('IO',0);
 iPos = get_param(gcb,'Position');
 iWidth=iPos(3)-iPos(1);
 iHeight=iPos(4)-iPos(2);
 [logoX, logoY] = xlogo(iPos);
 if (show_out)
     old = find_system(gcb, 'LookUnderMasks', 'all', 'Name',   'Terminator');
     if (length(old) > 0)
         replace_block(gcb, 'Name', 'Terminator', 'OutPort', 'noprompt');
         set_param([gcb '/Terminator'], 'Name', 'OutPort');
     end
     portdir = 'output';
     portstr = 'dbl';
 else
     old = find_system(gcb, 'LookUnderMasks', 'all', 'name', 'OutPort');
     if (length(old) > 0)
         replace_block(gcb, 'Name', 'OutPort', 'Terminator', 'noprompt');
         set_param([gcb '/OutPort'], 'Name', 'Terminator');
     end
     portdir = 'input';
     portstr = '';
 end

Documentation Tab

Mask type Non-Memory-Mapped Output Port Mask Description Port Name: "PMOD0" Port Type: Boolean

14. Save.

15. Now you can drag the block from the library and use as you would a NMM created automatically by System Generator. Ref http://myfpgablog.blogspot.com/2009/12/sysgen-create-new-hwcosim-target-with.html to see how to do this.

Hope this helps.

Regards,

William Knox