Propagation of signals in RF Data Converter block in simulation and on hardware

Dear all,

I am using SoC Blockset to design a simple receiver using AMD Zynq Ultrascale+ ZCU111 evaluation board. The relevant model is attached.

The word lengths for data converters on this board are 14bit for DAC and 12bit for ADC. That means, that when a digital code Ddac is fed to DAC, and the converted signal is loopbacked to ADC, the new digital code for this signal will be Dadc = Ddac/4.

However, if we simulate the model attached, we can see, that even though the HW board is set to be ZCU111, the output of adcT0Ch0Data is the same as the input to dacT0Ch0Data, of the length of 14 bits. This does not make sense to me, as I have two possibilities then:

1) Treat this signal from ADC as 14-bit. Then the logic in simulation is ok, but when I generate the code, real ADC wordlength will be 12-bit, so the design will not be suitable.

2) Convert this signal to 12-bit. for example the output of ADC is 00011011101010, I convert it to 12bit and get the result of 000110111011 (last bit becomes 1). But then on the HW, when I will convert the signal like this, the wordlength will be truncated from 12 to 10.

Could you, please, explain, why are they same and how a design with RF Data Converter set up like in the attached model will behave on the board when deployed?

Thank you!

UDP: RFDC must be set to "behavioral" mode - this makes the propagation more realistic, and signal from ADC actually is supposed to be a 16bit long, even though the resoilution is only 12bit (the 12bit ADC result is alligned to 16bit word, so there is no need to extract the 12bits).

Answer 1

[Sanjay Boorle]

Hi @Sergei,

In the attached model, the RFDC simulation is set to "Pass-through", in this mode the ADC output is same as the DAC input. Can you set it to "Behavioral" mode and try again.

Thanks.

[Sergei]

Hello, @Sanjay Boorle,

Thank you a lot! Now the ADC signal is 12bit long, that is exactly the thing I was asking for.

Best regards

[Sergei]

Hello again, @Sanjay Boorle,

thank you for your answer again. Now I have made a model with "Behavioral" mode for RFDC. The model is attached. The results are interesting:

The signal ADC_Data_converted_12 is the signal received afrom adcT0Ch0Data and converted to fixdt(1, 12, 10), which is expected to be approximately the same as the Signal_Donwsampled. But if we treat the ADC_Data as a 16bit signal (which it is not in HW), then the signal looks exactly how it is supposed to. What am I doing wrong?

[Sergei]

The test model

[Sanjay Boorle]

Hi @Sergei,

Even though the resolution of DAC is 14-bits and ADC is 12-bits, the data width of the streaming interface in 16-bit. In Xilinx doc (pg269), they mentioned that "14-bit RF-DAC resolution with 16-bit digital signal processing path; the data is MSB-aligned to 16 bits" and "Gen 1/Gen 2: 12-bit RF-ADC resolution, with 16-bit digital signal processing datapath; each 12-bit data stream is MSB-aligned to 16-bit samples at the output of the RF-ADC core before passing to the DDC block".

So, in the ADC output, all 16-bits are considered valid and you don't need to extract 12-bits. You can also refer table "Table 75: RF-ADC and RF-DAC Word Interface" under "Ch 6 Example Design" in ver 2.5 https://docs.amd.com/v/u/2.5-English/pg269-rf-data-converter (for some reason, not available in latest version).

Hope this helps.

Thanks,

Sanjay

[Sergei]

Good to hear from you again, @Sanjay Boorle. Thank you a lot! I think this a very helpful answer and I understand by gap now. I was absolutely sure that the output of ADC must be a 12-bit digital code. Will read the document you sent me - I have never paid attention to it for some reason. Thank you again!