How does the PWM generator(3-level) block in Simulink work?

I am simulating a three-phase NPC inverter, which uses the Phase disposition PWM as its PWM. Simulink also has this particular PWM in the form of PWM generator(3-level) block, however I am quite confused about its operation. From my understanding, PWM signals are generated between the reference signal and carrier signal. The amplitude of the reference signal has to be smaller than the carrier signal, otherwise it will be overmodulated.

I observed that the carrier signal in PWM generator(3-level) block uses a carrier signal of maximum value equals to 1 or -1(triangle generator). However, I placed a scope to measure the Uref and observed that the amplitude is 40 to -40!. Yet, the system can still produce a good sinuisoidal inverter current.

Meanwhile when I use a divide block(divde by the grid voltage for normalization) to reduce this magnitude to 1/-1, the Uref signal becomes distorted and the subsequent inverter current is also affect. Why is this the case?? Even when i recreated the PWM generator(3-level) block by myself, the same results are generated, as if the reference signal can be overmodulated and acceptable. Does anybody know about this problem?? However, I have a feeling that the inverter voltage after using the divide block is more correct? This is just my hunch.

Additional note, for the screenshots of the inverter current, the top waveform is a NOT grid voltage, it is the inverter voltage. I made a mistake in the labelling.

Answer 1

[Sabin]

For linear operation of this block, the magnitude of Uref must be between −1 and +1 as per the documentation page. If the Uref is out of range (e.g., -40 to 40), the inverter output current may still appear sinusoidal due to the filtering effect of the load and system inductance, which smooths out the high frequency switching harmonics. The information provided makes it difficult to point to a specific root cause, attaching a model can help.