C28x I2C Receive
Configure inter-integrated circuit (I2C) module to receive data from I2C bus
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C2000 Microcontroller Blockset / F2838x / C28x
C2000 Microcontroller Blockset / F28M35x / C28x
C2000 Microcontroller Blockset / F28M36x / C28x
The I2C Receive block configures the inter-integrated circuit (I2C) module to receive data from the two-wire I2C serial bus. The I2C Receive block supports I2C bus communication between the processor and external peripherals or other controllers. The block can run in either peripheral or controller mode.
When the I2C module is configured as controller, the module receives data from a peripheral. When the I2C module is configured as a peripheral, the module receives data from the controller. Configure the I2C module by navigating to Configuration Parameters > Hardware Implementation > Target hardware resources.
To read data from a peripheral, send the address of the register to be read using the I2C Transmit block to the peripheral. Ensure that the data is sent from the Tx FIFO to the peripheral before the data is read from the peripheral using the I2C Receive block. For more information, see Using the I2C Bus to Access Sensors.
SAR — Peripheral address register value
The peripheral address register value.
This port appears only when Peripheral address
source is set to
RD — Received data from I2C bus
scalar | vector
The data read from the I2C bus.
status — I2C communication status
Status values from the I2C status register (I2CSTR).
This port appears only when Output receiving status is selected.
Module — Module for communication
I2C_A (default) |
The I2C module to be used for communication. The number of I2C modules supported varies across different C2000™ processors.
Addressing format — Address format for communication
7–Bit addressing (default) |
10–Bit addressing |
Free data format
The address format for communication. The diagram shows the format for each option. The I2C Receive block sets the R/W bit to 0.
S — Start bit
R/W — Read/Write
ACK — Acknowledge
P — Stop bit
MSB — Most significant bit
LSB — Least significant bit
Peripheral address source — Peripheral address source of I2C peripheral
Specify via dialog (default) |
The method for setting the peripheral address register of the I2C peripheral.
Peripheral address register — Peripheral address register value
80 (default) | scalar
Enter a 7- or 10-bit peripheral address according to the addressing format selected.
This parameter appears only when Peripheral
address source is set to
Specify via dialog.
Bit count — Bit count for communication
8 (default) | integer in [1 8]
The number of bits in the data byte received by the I2C module.
Read data length — Length of received data
1 (default) | scalar
The number of Data type the block receives (not
bytes). If this parameter is set to more than
output will be a vector.
Initial output — Value of I2C node output to model
0 (default) | scalar | vector
The value the I2C node outputs to the model before it has received data.
By default, the block outputs
0 if the I2C value is not
Set NACK bit — NACK bit during I2C acknowledge cycle
off (default) |
Generates a no-acknowledge bit (NACK) during the I2C acknowledge cycle and ignores new bits from the transmitting I2C node.
Enable stop condition — Stop message to I2C Transmit block
off (default) |
Enables the I2C Receive block (controller) to send a stop message to the I2C Transmit block (peripheral).
Output receiving status — Indicates when I2C Receive block receives message
off (default) |
Enables the status output port, which indicates when the I2C Receive block receives a message.
Sample time — Frequency at which data is read from I2C device
0.001 (default) |
–1 | scalar
Sample time for the block in seconds. To execute this block
asynchronously, set this parameter to
Data type — Type of data in data vector
int8 (default) |
Sets the data type of the data received. If the size of the received data is less than 8 bits, then the data is right-justified.