verify

Assess logical expression and log result

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Syntax

verify(expression)
verify(expression,errorMessage)
verify(expression,identifier,errorMessage)

Description

verify(expression) evaluates the scalar logical expression to true or false.

example

verify(expression,errorMessage) returns the specified error message if the scalar logical expression fails. If you run the test in the Test Manager, the error message appears in the simulation log. If you run the test outside the Test Manager, the message appears in the Diagnostic Viewer. Specify errorMessage as a character array, which you can format using sprintf. You cannot use sprintf formatting in strings or character arrays in Stateflow® charts.

Note

In a real-time environment, verify statement failures do not produce warnings. If you run a real-time test case in the Test Manager, the Verify Statements section displays the failures for the test case results. You can also access information about verify runs using getVerifyRuns.

If you run test iterations in fast restart simulation mode, verify statements do not print information, errors, or warnings to the Diagnostic Viewer, the Logs section in the Test Manager, or test reports.

example

verify(expression,identifier,errorMessage) uses the identifier as a label for the test results. If you run the test in the Test Manager the identifier is used as the signal label test results. If you run the test outside the Test Manager, the label appears in the Simulation Data Inspector or, for a failure, in the Diagnostic Viewer. Specify identifier as a character array that has at least two colon-separated MATLAB® identifiers.

example

Examples

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This verify statement evaluates two expressions:

verify(x > y && z > 10)

If this verify statement fails, it returns an error message that lists the values of x, y, and z.

verify(x > y && z > 10,'x, y, and z are %d,%d,%d',x,y,z)

The result of this verify statement is prefaced by the label, TestReq1:bothGreater and, if the test fails, the error message.

verify(x > y && z > 10,'TestReq1:bothGreater',...
   'x, y, and z are %d,%d,%d',x,y,z)

To only evaluate logical expressions when a statement meets multiple conditions, define the verify statement by using an if statements.

if u1 == false && u2 == false
  verify(x1 == false && x2 == false)

The second step in the Scenario1 state of this Stateflow chart verifies that the target equals 60.

Stateflow chart with verify statement

Limitations

  • You cannot use verify statements in:

    • Test Sequence blocks that use continuous-time updating. Test Sequence block data can depend on factors such as the solver step time. Continuous-time updating can cause differences in when block data and verify statements update, which can lead to unexpected verify statement results. If your model uses continuous time and you use verify statements in a Test Sequence or Test Assessment block, consider explicitly setting a discrete block sample time.

    • Moore, Mealy, Discrete Event, or continuous charts

    • Charts that use C as the action language

    • Bind actions in a chart

    • Transition or condition actions in a chart

    • MATLAB functions, graphical functions, or truth tables in a chart

    • MATLAB Function or Truth Table blocks

    • Simulations in rapid accelerator mode

    • Code generation targets other than Simulink® Real-Time™ and HDL Verifier™

    • Standalone Stateflow charts

  • You cannot use verify as a condition immediately after when in a When decomposition because verify statements do not produce outputs. You can use verify statements as actions in When decomposition steps. See Verify Model Simulation by Using when Decomposition.

  • If you use parallel test execution to run your tests, and use a verify statement in your test, you cannot use the Highlight in Model button in the Test Manager.

Tips

  • You can use verify statements in Test Sequence and Test Assessment blocks and in Stateflow charts. A Stateflow license is required to use a chart. verify statements in charts are supported in the same locations, execution modes, and for the same code generation targets as the Test Sequence block.

  • You can use verify statements with or without a test case. If the model does not include a test case, the results appear in the Simulation Data Inspector. If the model includes a test case, the results appear in the Test Manager.

  • To verify multiple expressions in a single time step, define the verify statements in the same test step or add substeps and add a verify statement to each substep. See Manage Test Steps.

  • When comparing floating-point data in verify statements, consider the precision limitations associated with floating-point numbers. If you need to use floating-point data, define a tolerance for the verification. For example, instead of verify(x == 5), verify x within a tolerance of 0.001: 

    verify(abs(x-5) < 0.001)
    For more information, see Floating-Point Numbers.

  • To reduce the transfer of data when you simulate a model on target hardware, you can choose to log only tested verify statement results and display only pass and fail results in the Test Manager and Simulation Data Inspector.

    To log only pass and fail verify results, on the Tests or Harness tab, in the Test Cases section, click Suppress Untested Results. Alternatively, you can use set_param to set the logOnlyTestedVerifyResults parameter to 'on'. For example, to log only tested verify statement results for the model myModel:

    set_param(myModel,'logOnlyTestedVerifyResults','on')
    When you select this option, the setting applies to all Test Sequence or Chart blocks in the model. The setting does not apply when using HDL Verifier.

Version History

Introduced in R2016a

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See Also

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