Use resettable subsystems when you want to conditionally reset the states of all blocks within a subsystem to their initial condition. A resettable subsystem executes at every time step but conditionally resets the states of blocks within it when a trigger signal occurs at the reset port. This behavior is similar to the reset behavior of blocks with reset ports, except that a resettable subsystem resets the states of all blocks inside it.
Using resettable subsystems over other methods of resetting states of your block or subsystem has these advantages:
When you want to reset the states of multiple blocks in a subsystem, displaying and connecting the reset port of each block is cumbersome and makes the block diagram hard to read. Instead, place all the blocks in a resettable subsystem and configure the Reset block in the subsystem.
Some blocks, such as the Discrete State-Space block, have states but do not have reset ports. You cannot reset these blocks individually, and you must reset the subsystem they are inside. In such cases, it is useful to place these blocks in a resettable subsystem.
You can also reset blocks in enabled subsystems by setting the States
when enabling parameter on the enable port to
reset. However, for this behavior, you must disable the
subsystem and then reenable it at a later time step. To reset your block states at the
same time step, use resettable subsystems. For more information, see Comparison of Resettable Subsystems and Enabled Subsystems.
All blocks in a resettable subsystem must have the same sample time, and they execute at every sample time hit of the subsystem. Resettable subsystems and the model use a common clock.
This model shows that the behavior of block reset ports and resettable subsystems is the same. A resettable subsystem enables you to reset the states of all blocks inside it. The resettable subsystem contains an integrator block that is configured similar to the root-level Integrator block, but the block does not have a reset port. The subsystem resets the states of the integrator block inside it in the same manner as the reset port of the Integrator block. You can see this behavior by running the model and viewing the output in the scope.
If you set States when enabling for the Enable block
reset, the enabled subsystem resets the states of all blocks
in the subsystem. However, you must disable the subsystem for at least one time step and
then reenable it for the states to reset.
In contrast, resettable subsystems always execute and reset the states of their blocks instantaneously.
This model shows the difference in the execution behavior of these subsystems. It
contains an enabled subsystem and a resettable subsystem whose control ports are connected
to pulse generator. The resettable subsystem is set to reset on the rising edge of the
control signal, and the enabled subsystem has the States when enabling
parameter set to
reset in the enable port.
The subsystems contain identical Discrete-Time Integrator blocks, whose input is the Constant block at the root level of the model. The figure shows the contents of the resettable subsystem.
The figure shows the simulation output.
When the control signal is 0, the enabled subsystem is disabled and the integrator does not change its output while the resettable subsystem is executing. The rising edge of the control signal triggers the reset port of the resettable subsystem and enables the enabled subsystem. Both subsystems reset their states at this time step.
Notice that the enabled subsystem is disabled for at least one time step before its states can are reset. The resettable subsystem does not have this limitation.