To capture signal data from a simulation, usually you can use signal logging. Mark the signals that you want to log and enable signal logging for the model. For details, see Configure a Signal for Logging and Enable Signal Logging for a Model.
For a summary of other approaches to capture signal data, see Export Simulation Data.
To collect and use signal logging data, perform these tasks.
One approach for testing parts of a model as you develop it is to mark a superset of signals for logging and then override signal logging settings to select different subsets of signals for logging. You can use the Signal Logging Selector or a programmatic interface. See Override Signal Logging Settings.
Use this approach to log signals in models that use model referencing. For an example, see Viewing Signals in Model Reference Instances.
With the basic signal logging workflow, you can specify additional options related to the data that signal logging collects and to how that data is displayed. You can:
Specify a name for the signal logging data for a signal. See Specify Signal-Level Logging Name.
Control how much data the simulation generates for a signal. See Limit Data Logged.
Review the signal logging configuration for a model. See View the Signal Logging Configuration.
Specify the samples for export for models with variable-step solvers. See Samples to Export for Variable-Step Solvers.
Signal logging in rapid accelerator mode does not log the following kinds of signals. When you update or simulate a model that contains these signals, Simulink® displays a warning that those signals are not logged.
Signals inside Stateflow® charts
Signals that use a custom data type
If you set the Configuration Parameters > Solver > Periodic sample time constraint parameter to
Ensure sample time independent, you
cannot use signal logging in rapid accelerator mode.
Rapid accelerator mode supports signal logging, with the requirements and limitations described in Signal Logging in Rapid Accelerator Mode.
Top-model and Model block software-in-the-loop (SIL) and processor-in-the-loop (PIL) simulation modes support signal logging. For a description of limitations, see Top-Model SIL/PIL Limitations (Embedded Coder) and Model Block SIL/PIL Limitations (Embedded Coder).
Array of buses signals support signal logging, with the requirements described in Import Array of Buses Data.
You cannot log bus signals directly in For Each subsystems.
You cannot log a signal inside a referenced model that is inside a For Each subsystem if either of these conditions exists:
The For Each subsystem is in a model simulating in rapid accelerator mode.
The For Each subsystem itself is in a model referenced by a Model block in accelerator mode.
You cannot log signals that feed Function-Call subsystems or Action subsystems.
You cannot log an input signal to a Merge block. You can log a Merge block output signal.
For Integrator and Discrete-Time Integrator blocks that have the Show state port parameter enabled, you cannot log the state port signal.
If you configure a bus signal or bus element for signal logging that is an input to a subsystem, you cannot automatically refactor the subsystem interface to use In Bus Element and Out Bus Element blocks. For details about that refactoring, see Simplify Bus Interfaces in Subsystems.
You cannot log local data in Stateflow Truth Table blocks.