Detect Fall Negative

R2026b

Detect falling edge when signal value decreases to strictly negative value, and its previous value was nonnegative

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Detect Fall Negative block

To add a block to a model, double-click the canvas and start typing the block name. Then, select the block from the list.

Libraries:
Simulink / Logic and Bit Operations
HDL Coder / Logic and Bit Operations

Description

The Detect Fall Negative block determines if the input is less than zero, and its previous value is greater than or equal to zero.

This block supports only discrete sample times.

Examples

Detect Fall to Negative Signal Values

This example shows how to detect when a signal value decreases to a strictly negative value from a value that was greater than or equal to zero.

Ports

For more information, see Data Types Supported by Simulink.

Input

Port_1 — Input signal

signal value

Input signal, specified as a scalar, vector, or matrix.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated

Output

Port_1 — Output signal

0 | 1

Output signal, true (equal to 1) when the input signal is less than zero, and its previous value was greater than or equal to zero; false (equal to 0) when the input signal is greater than or equal to zero, or if the input signal is negative, its previous value was also negative.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | bus

Parameters

Initial condition — Initial condition for the previous input

0 (default) | scalar | vector

Set the initial condition of the Boolean expression U/z < 0.

Programmatic Use

Block Parameter: vinit

Type: character vector

Values: scalar | vector

Default:'0'

Input processing — Specify sample- or frame-based processing

Elements as channels (sample based) (default) | Columns as channels (frame based)

Specify whether the block performs sample- or frame-based processing:

• Columns as channels (frame based) — Treat each column of the input as a separate channel (frame-based processing).

  Note

  Frame-based processing requires a DSP System Toolbox™ license.

  For more information, see Sample- and Frame-Based Concepts (DSP System Toolbox).

• Elements as channels (sample based) — Treat each element of the input as a separate channel (sample-based processing).

Use Input processing to specify whether the block performs sample- or frame-based processing. For more information about these two processing modes, see Sample- and Frame-Based Concepts (DSP System Toolbox).

Programmatic Use

Block Parameter: InputProcessing

Type: character vector

Values: 'Columns as channels (frame based)' | 'Elements as channels (sample based)'

Default: 'Elements as channels (sample based)'

Output data type — Data type of the output

boolean (default) | uint8

Set the output data type to boolean or uint8.

Programmatic Use

Block Parameter: OutDataTypeStr

Type: character vector

Values: 'boolean' | 'uint8'

Default: 'boolean'

Block Characteristics

Data Types	Boolean | double | fixed point | integer | single
Direct Feedthrough	yes
Multidimensional Signals	yes
Variable-Size Signals	yes
Zero-Crossing Detection	no

Programmatic Use: Add Block

To add the block programmatically, use the add_block function with one of these library block paths as the source.

"simulink/Logic and Bit Operations/Detect Fall Negative"

"hdlsllib/Logic and Bit Operations/Detect Fall Negative"

Example: add_block("simulink/Logic and Bit Operations/Detect Fall Negative","myModel/myBlock",MakeNameUnique="on")

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

Generated code relies on memcpy or memset functions (string.h) under certain conditions.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays in the design. Distributed pipelining does not redistribute these registers. The default value is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see OutputPipeline (HDL Coder).
SynthesisAttributes	Specifies the synthesis attributes for the blocks and block output signals in the model. The generated HDL code contains these attributes. For more information, see SynthesisAttributes (HDL Coder).

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a

R2026a: Specify synthesis attributes for blocks and block output signals

Use the SynthesisAttributes HDL block property to specify the synthesis attributes for the block and its output signals. HDL Coder includes these attributes in the generated HDL code.