CEI 56G-VSR Compliance Kit

Characterize and validate the performance of a CEI 56G-VSR channel design.

CEI 56G-VSR is a common electrical interface (CEI) implementation agreement (IA) that supports 56 Gb/s over “Very Short Reach” (VSR) optical or electrical chip-to-module applications. The CEI-56G-VSR Clause is part of the Common Electrical I/O 3.1 Implementation Agreement.

The interface relies on PAM4 modulation to increase the bandwidth in 28 GB/s channels. PAM4 modulation can transmit 4-bits per cycle instead of only 2 bits per cycle for NRZ modulation. Theoretically, changing the modulation for signaling will double the bandwidth, so that 28 GB/s compliant channels can run at 56 Gb/s. However, in practice, the design of these interfaces can be challenging when attempting to double the bandwidth using PAM4 modulation.

This kit is designed for bidirectional analysis of a host board to an optical module board. The total channel loss at Nyquist or Fb/2 is approximately 10 dB. The VSR channel consists of a host board connected with a mated connector to a module board that represents the interconnection between the transmitting and receiving data across the channel. The kit contains sheets that include the specific host and/or module board design and characterization. Network characterization is set up for insertion and return loss testing to the compliance masks, channel FEXT/NEXT crosstalk is included in multi-channel sheets to measure the effects on BER compliance and RX stress testing.

This kit enables you to insert a channel design and characterize and validate its performance using the specification masks to determine if the channel has a high confidence of success. If the channel does not meet the compliance masks or BER estimates, further investigation or redesign, along with simulation, will need to be performed to determine possible changes to meet compliance. In addition, not all compliance metrics can be simulated and thus will need to be measured in a laboratory environment.

Open CEI 56G-VSR Kit

Open the CEI 56G-VSR kit in the Serial Link Designer app using the openSignalIntegrityKit function.

openSignalIntegrityKit("CEI_56G_VSR");

Kit Overview

• Project Name: CEI_56G_VSR

• Interface Name: CEI_56G_VSR

• Target Operating Frequency: From 36 Gb/s to 58 Gb/s (PAM4 encoding) (UI = 55.55 ps to 34.48 ps)

The CEI 56G-VSR kit defines two schematic sets. Schematic sheets are included for testing a CEI 56G-VSR channel with mated connector to a module board. The masks provided in this kit are given in the CEI 56G-VSR specification [1].

• Compliance – All compliance host-to-module or module-to-host simulations

• MCB_HCB_Characterization – Compliance board network simulations.

For more information about the CEI 56G-VSR channel compliance schematics, transfer net properties, and compliance rules, refer to the document CEI_56G_VSR.pdf that is attached to this example as a supporting file.

References

[1] CEI-56G: Paving the Way for 100 Gigabit, OIF Forum Whitepaper, OIF_CEI-56G_WP_Final.pdf