Model Delays in Multi-Stage Ring Oscillator
This example shows how to explore the range of options for simulating the analog applications of digital circuits. Using the blocks from the Mixed-Signal Blockset™, you can model delays in each stage of a three-stage ring oscillator. The delays in each stage determine the output frequency of the oscillator, making the accurate modeling of these delays essential to the simulation of the circuit.
This example walks you through the workflow using these steps:
Logic Timing Simulation — Produce digital waveforms with accurate timing by using variable step discrete sampling
Digital Timing Using Fixed Step Sampling — Model the three-stage ring oscillator using a combination of fixed step and variable step discrete sample times.
Digital Timing Using Solutions to Ordinary Differential Equations — Model the three-stage ring oscillator using models defined by ordinary differential equations (ODE)
