Export of Verification IP
Generate testbench components and verification IP from MATLAB® or Simulink®. Export components into Universal Verification Methodology (UVM) or SystemVerilog environments. These models run natively in your HDL simulator.
Generate SystemVerilog Direct Programming Interface (DPI) components from MATLAB and Simulink. For more information, see SystemVerilog DPI Component Generation.
Generate UVM components or environments from MATLAB and Simulink. For more information, see UVM Component Generation Overview.
Export SystemC™ TLM-compatible transaction-level models from Simulink. For more information, see TLM Component Generation.
To use this functionality, download and install the ASIC Testbench for HDL Verifier add-on.
Categories
- UVM Generation
Generate UVM components from Simulink subsystems or MATLAB functions
- DPI Generation for Simulink Subsystem
Generate SystemVerilog DPI component from Simulink subsystem
- DPI Generation for MATLAB Code
Generate SystemVerilog DPI component from MATLAB code
- Transaction Level Model Generation
Generation of SystemC TLM virtual prototypes
