setNumberofTriggerStages

Configure number of trigger stages for capturing data

Since R2024a

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Syntax

setNumberofTriggerStages(hub,N)
setNumberofTriggerStages(hub,N,DataCaptureName=dataCaptureIPName)

Description

Add-On Required: This feature requires the HDL Verifier Support Package for AMD FPGA and SoC Devices add-on.

setNumberofTriggerStages(hub,N) configures the number of trigger stages, N, for capturing data for the first data capture IP. hub is customized data capture hub object.

example

setNumberofTriggerStages(hub,N,DataCaptureName=dataCaptureIPName) configures the number of trigger stages, N, for a data capture IP specified by dataCaptureIPName.

Examples

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This example uses a customized data capture hub object, hub, that connects with two data capture IPs. The first data capture IP is datacapture1 and the second data capture IP is datacapture2.

Set number of trigger stages to 2 for the datacapture1 IP.

setNumberofTriggerStages(hub,2);

Set number of trigger stages to 2 for the datacapture2 IP.

setNumberofTriggerStages(hub,2,DataCaptureName="datacapture2");

Input Arguments

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Data capture hub object that interacts with each data capture IP, specified as a dataCaptureHub object.

Total number of trigger stages in which you want to capture the data, specified as an integer from 1 to M, where M is set by the Max trigger stages parameter of the FPGA Data Capture Component Generator tool.

Name of the data capture IP, specified as a character vector or string scalar. The default value for this argument is "generatedIPName1", where generatedIPName1 is the name of the first data capture IP set by the Generated IP name parameter of the FPGA Data Capture Component Generator tool.

Version History

Introduced in R2024a

See Also

Objects

Tools