Connection

How signals are connected when the module is instantiated

Model Configuration Pane: SystemVerilog DPI / SystemVerilog Ports

Description

Select how signals are connected when the module is instantiated.

Port list (default) | Interface

Default: Port list

Port list: Generate a SystemVerilog module with a port list in the header, representing its interface.
Interface: Generate a SystemVerilog interface, and a module using that interface.

Parameter: DPIPortConnection

Type:

Values:Port list| Interface

Default:Port list

Introduced in R2013b

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