Set up a writable working folder outside your MATLAB® installation
folder to store files that will be generated as you complete your
tutorial work. The tutorial instructions assume that you create the
hdlfilter_tutorials on drive C.
This tutorial guides you through the steps for designing an optimized quantized discrete-time FIR filter, generating Verilog code for the filter, and verifying the Verilog code with a generated test bench.
This section assumes that you are familiar with the MATLAB user interface and the Filter Designer.
Start the MATLAB software.
Set your current folder to the folder you created in Create a Folder for Your Tutorial Files.
Start the Filter Designer by entering the
filterDesigner command in the
MATLAB Command Window. The Filter Design & Analysis Tool dialog
In the Filter Design & Analysis Tool dialog box, set the following filter options:
|Filter Order||Minimum order|
These settings are for the default filter design that the Filter Designer creates for you. If you do not have to change the filter, and Design Filter is grayed out, you are done and can skip to Quantize the FIR Filter.
Click Design Filter. The Filter Designer creates a filter for the specified design. The following message appears in the Filter Designer status bar when the task is complete.
Designing Filter... Done
For more information on designing filters with the Filter Designer, see the DSP System Toolbox™ documentation.
You must quantize filters for HDL code generation. To quantize your filter,
Open the FIR filter design you created in Design the FIR Filter in Filter Designer if it is not already open.
Click the Set Quantization Parameters button in the left-side toolbar. The Filter Designer displays a Filter arithmetic menu in the bottom half of its dialog box.
the list. Then select
Specify all from
the Filter precision list. The Filter Designer
displays the first of three tabbed panels of quantization parameters
across the bottom half of its dialog box.
Use the quantization options to test the effects of various settings on the performance and accuracy of the quantized filter.
Set the quantization parameters as follows:
|Coefficients||Numerator word length|
|Best-precision fraction lengths|
|Use unsigned representation|
|Scale the numerator coefficients to fully utilize the entire dynamic range|
|Input/Output||Input word length|
|Input fraction length|
|Output word length|
|Filter Internals||Rounding mode|
|Accum. word length|
For more information on quantizing filters with the Filter Designer, see the DSP System Toolbox documentation.
After you quantize your filter, you are ready to configure coder options and generate Verilog code for the filter. This section guides you through starting the UI, setting options, and generating the Verilog code and a test bench for the FIR filter you designed and quantized in Design the FIR Filter in Filter Designer and Quantize the FIR Filter.
Start the Filter Design HDL Coder™ UI by selecting Targets > Generate HDL in the Filter Designer dialog box. The Filter Designer displays the Generate HDL dialog box.
the Language option, as shown in the following
In the Name text box of the Target pane,
replace the default name with
optfir. This option
names the Verilog module and the file that contains the Verilog code
for the filter.
In the Filter architecture pane, select the Optimize for HDL option. This option is for generating HDL code that is optimized for performance or space requirements. When this option is enabled, the coder makes tradeoffs concerning data types and might ignore your quantization settings to achieve optimizations. When you use the option, keep in mind that you do so at the cost of potential numeric differences between filter results produced by the original filter object and the simulated results for the optimized HDL code.
CSD for the Coefficient
multipliers option. This option optimizes coefficient multiplier
operations by instructing the coder to replace them with additions
of partial products produced by a canonical signed digit (CSD) technique.
This technique minimizes the number of addition operations required
for constant multiplication by representing binary numbers with a
minimum count of nonzero digits.
Select the Add pipeline registers option. For FIR filters, this option optimizes final summation. The coder creates a final adder that performs pairwise addition on successive products and includes a stage of pipeline registers after each level of the tree. When used for FIR filters, this option can produce numeric differences between results produced by the original filter object and the simulated results for the optimized HDL code.
The Generate HDL dialog box now appears as shown.
Select the Global settings tab of the UI. Then select the General tab of the Additional settings section.
In the Comment in header text box, type
- Optimized FIR Filter. The coder adds the comment to the
end of the header comment block in each generated file.
Select the Ports tab of the Additional settings section of the UI.
Change the names of the input and output ports. In
the Input port text box, replace
In the Output port text box, replace
Clear the check box for the Add input register option. The Ports pane now looks as shown.
Click the Test Bench tab in the
Generate HDL dialog box. In the File name text
box, replace the default name with
option names the generated test bench file.
In the Test Bench pane, click the Configuration tab. Observe that the Error margin (bits) option is enabled. This option is enabled because previously selected optimization options (such as Add pipeline registers) can potentially produce numeric results that differ from the results produced by the original filter object. You can use this option to adjust the number of least significant bits the test bench ignores during comparisons before generating a warning.
In the Generate HDL dialog box, click Generate to start the code generation process. When code generation completes, click Close to close the dialog box.
The coder displays the following messages in the MATLAB Command Window as it generates the filter and test bench Verilog files:
### Starting Verilog code generation process for filter: optfir ### Generating: C:\hdlfilter_tutorials\hdlsrc\optfir.v ### Starting generation of optfir Verilog module ### Starting generation of optfir Verilog module body ### HDL latency is 8 samples ### Successful completion of Verilog code generation process for filter: optfir ### Starting generation of VERILOG Test Bench ### Generating input stimulus ### Done generating input stimulus; length 3429 samples. ### Generating Test bench: C:\hdlfilter_tutorials\hdlsrc\optfir_tb.v ### Please wait ... ### Done generating VERILOG Test Bench
As the messages indicate, the coder creates the folder
your current working folder and places the files
Observe that the messages include hyperlinks to the generated code and test bench files. By clicking these hyperlinks, you can open the code files directly into the MATLAB Editor.
The generated Verilog code has the following characteristics:
Verilog module named
Registers that use asynchronous resets when the reset signal is active high (1).
Generated code that optimizes its use of data types and eliminates redundant operations.
Coefficient multipliers optimized with the CSD technique.
Final summations optimized using a pipelined technique.
Ports that have the following names:
|Clock enable input|
An extra register for handling filter output.
n is the coefficient number, starting
is used when zeros are concatenated:
'0' & '0'...
'_process' is appended
to sequential (
begin) block names.
The generated test bench:
Is a portable Verilog file.
Forces clock, clock enable, and reset input signals.
Forces the clock enable input signal to active high.
Drives the clock input signal high (1) for 5 nanoseconds and low (0) for 5 nanoseconds.
Forces the reset signal for two cycles plus a hold time of 2 nanoseconds.
Applies a hold time of 2 nanoseconds to data input signals.
Applies an error margin of 4 bits.
For a FIR filter, applies impulse, step, ramp, chirp, and white noise stimulus types.
Get familiar with the optimized generated Verilog code by opening
and browsing through the file
optfir.v in an ASCII
or HDL simulator editor:
Open the generated Verilog filter file
optfir. This line identifies the Verilog module, using the value
you specified for the Name option in the
Target pane. See step 3 in Configure and Generate Optimized Verilog Code.
Tutorial. This section of code is where the coder places the
text you entered for the Comment in header option. See
step 9 in Configure and Generate Optimized Verilog Code.
HDL Code. This section lists the coder options you modified in
Configure and Generate Optimized Verilog Code.
Filter Settings. This section of the VHDL code describes the
filter design and quantization settings as you specified in Design the FIR Filter in Filter Designer and Quantize the FIR Filter.
module. This line names the Verilog module, using the value you
specified for the Name option in the
Target pane. This line also declares the list of
ports, as defined by options on the Ports pane of the
Generate HDL dialog box. The ports for data input and output are named with
the values you specified for the Input port and
Output port options on the
Ports tab of the Generate HDL dialog box. See steps
3 and 11 in Configure and Generate Optimized Verilog Code.
input. This line and
the four lines that follow, declare the direction mode of each port.
Constants. This code
defines the coefficients. They are named using the default naming
the coefficient number, starting with 1.
Signals. This code defines
the signals of the filter.
sumvector1. This area of code declares the signals for
implementing an instance of a pipelined final adder. Signal declarations for
four additional pipelined final adders are also included. These signals are
used to implement the pipelined FIR adder style optimization specified with
the Add pipeline registers option. See step 7 in Configure and Generate Optimized Verilog Code.
reset. This code asserts
the reset signal. The default, active high (1), was specified. Also
note that the
process applies the default asynchronous
reset style when generating code for registers.
posedge. This Verilog
code checks for rising edges when the filter operates on registers.
sumdelay_pipeline_process1. This block implements the pipeline
register stage of the pipeline FIR adder style you specified in step 7 of
Configure and Generate Optimized Verilog Code.
output_register. This code writes the filter output to an output
register. The code for this register is generated by default. In step 12 in
Configure and Generate Optimized Verilog Code , you cleared the Add input register option, but
left the Add output register selected. Also note that
the process name
Output_Register_process includes the
data_out. This code
drives the output data of the filter.
This section explains how to verify the optimized generated Verilog code for the FIR filter with the generated Verilog test bench. This tutorial uses the Mentor Graphics® ModelSim® simulator as the tool for compiling and simulating the Verilog code. You can use other HDL simulation tool packages.
To verify the filter code, complete the following steps:
Start your simulator. When you start the Mentor Graphics ModelSim simulator, a screen display similar to the following appears.
Set the current folder to the folder that contains your generated Verilog files. For example:
If desired, create a design library to store the compiled Verilog modules. In the
ModelSim simulator, you can create a design library with the
Compile the generated filter and test bench Verilog files. In the
ModelSim simulator, you compile Verilog code with the
vlog command. The following commands compile the
filter and filter test bench Verilog code.
vlog optfir.v vlog optfir_tb.v
The following screen display shows this command sequence and informational messages displayed during compilation.
Load the test bench for simulation. The procedure for loading the test bench varies depending
on the simulator you are using. In the
ModelSim simulator, load the test bench for simulation with the
vsim command. For example:
The following display shows the results of loading
optfir_tb with the
Open a display window for monitoring the simulation as the test bench runs. In the Mentor Graphics ModelSim simulator, can use the following command to open a wave window and view the results of the simulation as HDL waveforms.
add wave *
The following wave window opens:
To start running the simulation, issue the start simulation command for your simulator. For
example, in the
ModelSim simulator, you can start a simulation with the
The following display shows the
command being used to start a simulation.
As your test bench simulation runs, watch for error messages. If error messages appear, interpret them as they pertain to your filter design and the HDL code generation options you selected. Determine whether the results are expected based on the customizations you specified when generating the filter Verilog code.
The following wave window shows the simulation results as HDL waveforms.