Generate HDL Code for Vendor-Specific FPGA Floating-Point Target Libraries
Mapping to a floating-point library enables you to synthesize your floating-point design without doing floating-point to fixed-point conversion. Eliminating the conversion step reduces the loss of data precision and enables you to model a wider dynamic range.
An FPGA floating-point library is a set of floating-point IP blocks that are optimized for synthesis on specific target hardware. These libraries are also referred to as vendor-specific floating point libraries because they target vendor-specific hardware. Altera® Megafunctions and Xilinx® LogiCORE IP are examples of these libraries. You can create a design and generate code that consists of HDL Coder™ native floating point (NFP) and vendor-specific FPGA point IP to more efficiently use resources on the FPGA, such as hardened DSP floating point adder or multiplier primitives, which allows you to fit a bigger design into the FPGA fabric. This mixed design is advantageous for large and complex models. Additionally, you can map blocks that are unsupported by the vendor-specific library to NFP and use the vendor library to map other blocks to vendor-specific floating point resources.
You can map your model to either the:
Native floating-point library. This option is the default mapping.
Native floating-point library and a vendor-specific floating point library. This is also called mixed-mode mapping.
When you map to both a native floating-point library and a vendor-specific floating-point library, HDL Coder maps to the vendor library IP wherever possible. The blocks that cannot be mapped to the vendor library then map to native floating-point library IP instead.
To see a list of HDL Coder blocks that support FPGA floating-point library mapping, see HDL Coder Support for FPGA Floating-Point Library Mapping.
Set Up Design for Mixed-Mode Mapping
To map your floating-point design to the native floating-point library and an Altera or Xilinx FPGA floating-point library:
Set up the path to your synthesis tool executable file by using
hdlsetuptoolpath. For example, to set the path to the
Altera Quartus IIsynthesis tool, enter:
hdlsetuptoolpath('ToolName','Altera Quartus II','ToolPath',... 'C:\altera\14.0\quartus\bin\quartus.exe');
Set the target device options for your Altera or Xilinx FPGA synthesis tool using
hdlset_param. For example, to set the synthesis tool as
Altera Quartus IIand chip family as
hdlset_param(model,'SynthesisToolChipFamily','Arria10', ... 'SynthesisToolDeviceName','10AS066H2F34E1SG', ... 'SynthesisToolPackageName','', ... 'SynthesisToolSpeedValue','')
Set up your Altera or Xilinx FPGA floating-point simulation libraries. See FPGA Simulation Library Setup.
Map to Native Floating-Point and FPGA Floating-Point Libraries
You can map your Simulink® model to floating-point target libraries from the Configuration Parameters dialog box or from the command line.
Map to Floating-Point Target Libraries from the Configuration Parameters Dialog Box
To map to the native floating point library and FPGA floating-point library:
In the Apps tab, select HDL Coder. In the HDL Code tab, click Settings.
In the HDL Code Generation > Floating Point pane, select Use Floating Point.
The Vendor Specific Floating Point Library parameter displays options based the synthesis tool you chose for your design. To use the Xilinx LogiCORE® IP, set the Vendor Specific Floating Point Library to
XILINXLOGICORE. For Altera megafunction IP, you can set Vendor Specific Floating Point Library to
When mapping to ALTERA FP FUNCTIONS, the target language must be VHDL.
You can customize the IP settings of the vendor-specific floating-point target library by using the
hdlcoder.FloatingPointTargetConfig.IPConfigobjects. For more information, see Customize Floating-Point IP Configuration.
To share floating-point IP resources, in the HDL Code Generation > Optimizationspane, in the Resource Sharing tab, select Floating-point IPs. The number of floating-point IP blocks that get shared depends on the SharingFactor that you specify on the subsystem.
Click OK. In the HDL Code tab, click Generate HDL Code.
Map to Floating-Point Target Libraries from the Command Line
To generate HDL code from the command line, you can use the
hdlcoder.createFloatingPointTargetConfig function to create a
floating-point IP configuration.
hdlcoder.createFloatingPointTargetConfigfunction to create a
hdlcoder.FloatingPointTargetConfigobject for the native floating-point library and a vendor-specific floating-point library. Then, use
hdlset_paramto save the configuration on the model.
For example, to create a floating-point target configuration for the native floating point and
ALTERA FP FUNCTIONSlibraries with the default settings and set the configuration to the
sfir_singlemodel, use these commands:
fpconfig = hdlcoder.createFloatingPointTargetConfig("NativeFloatingPoint",... VendorFloatingPointLibrary="ALTERAFPFUNCTIONS"); hdlset_param('sfir_single', 'FloatingPointTargetConfiguration', fpconfig);
You can customize the IP settings based on the floating-point library that you specify. For more information, see Customize Floating-Point IP Configuration.
makehdlfunction to generate HDL code from the DUT subsystem.
View Code Generation Reports of Floating-Point Library Mapping
To view information about the floating-point library mapping in the code generation report, before you begin code generation, enable the resource utilization report and optimization report. To learn how to generate these reports, see Create and Use Code Generation Reports.
To see the target floating-point block your design mapped to, the latency, and number of target-specific hardware resources, in the code generation report, select Target-specific Report.
Target Code Generation Report
In the code generation report, the Optimization Report > Target Code Generation section shows the optimization settings applied to the model. This section shows whether HDL Coder successfully generated floating-point target code.
Analyze Results of Floating-Point Library Mapping
You can get the latency information of the floating-point target IP from the generated model after HDL code generation. For example, consider this Add block in Simulink that has inputs of single data type.
After HDL code generation, the optimization report displays a link to the generated model. To see the floating-point target library that your Simulink block mapped to, open the generated model and double-click the DUT subsystem. The blocks that map to native floating point IP are light blue and include
NFPon the block mask. The blocks that map to the vendor-specific floating point IP are cyan and have initials associated with the vendor library on the block mask. In this example, the initials on the blocks that map to the
ALTERA FP FUNCTIONSlibrary display the initials
Double-click the Add block. The length of the delay block is the latency of the floating-point target IP.
To learn more about the generated model, see Generated Model and Validation Model.
To see your FPGA floating-point library mapping results, you can view the IP core files generated after HDL code generation.
HDL Coder checks and reuses existing generated IP core files, which takes less time when successively generating code for the same floating-point target IP.
- FPGA Floating-Point Library IP Mapping
- Design Model by Using HDL Coder Native Floating Point and Intel Hard Floating Point