Suppress out of bounds access errors by generating simulation-only index checks

Logic that runs during simulation time to prevent array indices from going out of bounds

Since R2022a

Model Configuration Pane: Global Settings / Advanced

Description

Enable or disable whether to generate additional logic that runs during simulation time to prevent array indices from going out of bounds. This option is available only when the Language option is set to VHDL. When you enable this option, a function is generated that uses a pragma to perform checks at simulation time. When the function encounters arrays, a function call is generated with the lower bound (zero) and the upper bound (size of array - 1) as the function parameters.

Settings

off (default) | on

Default: Off

on

Generate additional logic that runs during simulation time to prevent array indices from going out of bounds.

off

Do not generate additional logic that runs during simulation time to prevent array indices from going out of bounds.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property while generating HDL code for the symmetric_fir subsystem inside the sfir_fixed model by using either of these methods:

• Use hdlset_param to set the parameter on the model. Then generate HDL code by using the makehdl function.

  hdlset_param('sfir_fixed','SimIndexCheck','on')
  makehdl('sfir_fixed/symmetric_fir')

• Pass the property as an argument to the makehdl function.

  makehdl('sfir_fixed/symmetric_fir','SimIndexCheck','on')

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: SimIndexCheck

Type: character vector

Value: 'on' | 'off'

Default: 'on'

Version History

Introduced in R2022a