addFPGADataCaptureInterface

Class: hdlcoder.ReferenceDesign
Namespace: hdlcoder

Add and define FPGA Data Capture interface

Since R2025a

Syntax

addFPGADataCaptureInterface('AllowedConnectivityTypes',{'JTAG'})
addFPGADataCaptureInterface('AllowedConnectivityTypes',Connection_Types,'ManagerConnection',Manager_Connection,'ManagerAddressSegments',Manager_Address_Segments,'ManagerClockConnection',Manager_Clock_Connection,'ManagerResetConnection',Manager_Reset_Connection)
addFPGADataCaptureInterface('AllowedConnectivityTypes',{'JTAG'},'MemoryConnection',Memory_Connection,'MemoryAddressSegments',Memory_Address_Segments,'MemoryClockConnection',Memory_Clock_Connection,'MemoryResetConnection',Memory_Reset_Connection)
addFPGADataCaptureInterface('AllowedConnectivityTypes',Connection_Types,'ManagerConnection',Manager_Connection,'ManagerAddressSegments',Manager_Address_Segments,'ManagerClockConnection',Manager_Clock_Connection,'ManagerResetConnection',Manager_Reset_Connection,'MemoryConnection',Memory_Connection,'MemoryAddressSegments',Memory_Address_Segments,'MemoryClockConnection',Memory_Clock_Connection,'MemoryResetConnection',Memory_Reset_Connection)


Description

addFPGADataCaptureInterface('AllowedConnectivityTypes',{'JTAG'}) adds and defines an FPGA Data Capture interface to an hdlcoder.ReferenceDesign object. This argument enables data capture over a JTAG connection and uses internal BRAM resources to store captured data.

addFPGADataCaptureInterface('AllowedConnectivityTypes',Connection_Types,'ManagerConnection',Manager_Connection,'ManagerAddressSegments',Manager_Address_Segments,'ManagerClockConnection',Manager_Clock_Connection,'ManagerResetConnection',Manager_Reset_Connection) adds and defines an FPGA Data Capture interface to the hdlcoder.ReferenceDesign object with the options to connect to the AXI4 manager port of the processor. These arguments enable data capture over a processing system (PS) Ethernet or universal serial bus (USB) Ethernet connection and use internal BRAM resources to store captured data. In the HDL Workflow Advisor, HDL Coder™ adds connections specified by the Connection_Types argument to the FPGA Data Capture (HDL Verifier required) parameter in the Set Target Reference Design task.

addFPGADataCaptureInterface('AllowedConnectivityTypes',{'JTAG'},'MemoryConnection',Memory_Connection,'MemoryAddressSegments',Memory_Address_Segments,'MemoryClockConnection',Memory_Clock_Connection,'MemoryResetConnection',Memory_Reset_Connection) adds and defines an FPGA Data Capture interface to the hdlcoder.ReferenceDesign object with the options to connect to external DDR memory. These arguments enable capturing large data of up to two gigasamples by using the external DDR memory available on the FPGA board over a JTAG connection. When you specify these arguments, in the HDL Workflow Advisor, HDL Coder adds the External memory option to the FPGA Data Capture storage type parameter in the Generate RTL Code and IP Core task.

addFPGADataCaptureInterface('AllowedConnectivityTypes',Connection_Types,'ManagerConnection',Manager_Connection,'ManagerAddressSegments',Manager_Address_Segments,'ManagerClockConnection',Manager_Clock_Connection,'ManagerResetConnection',Manager_Reset_Connection,'MemoryConnection',Memory_Connection,'MemoryAddressSegments',Memory_Address_Segments,'MemoryClockConnection',Memory_Clock_Connection,'MemoryResetConnection',Memory_Reset_Connection) adds and defines an FPGA Data Capture interface to the hdlcoder.ReferenceDesign object with the options to connect to the AXI4 manager port of the processor and external DDR memory. These arguments enable capturing large data of up to two gigasamples by using the external DDR memory over a PS Ethernet or USB Ethernet connection.

Key Considerations

• This interface is supported only for the Intel^® and Xilinx^® synthesis tools.

• If you do not define this interface in the plugin_rd reference design definition file, the following syntax is applied by default:

  addFPGADataCaptureInterface('AllowedConnectivityTypes',{'JTAG'})

Input Arguments

Connection_Types — Connection types for data capture

{'JTAG'} (default) | cell array of character vectors

Connection types for data capture, specified as a cell array of character vectors. The supported connection types are:

• JTAG

• PL Ethernet

• PS Ethernet

• USB Ethernet

You can specify any or all of these connections if supported by the target board. In the HDL Workflow Advisor, HDL Coder adds connections specified by this argument to the FPGA Data Capture (HDL Verifier required) parameter in the Set Target Reference Design task.

For PS Ethernet and USB Ethernet connections, when you add the device tree to an hdlcoder.Board or hdlcoder.ReferenceDesign object by using the .dtb extension, follow the structure of the examples in Generate DTB File (HDL Verifier). When you use the .dts extension, you do not need to author the device tree, as it can be dynamically generated by HDL Coder. For more information about generating a device tree for the HDL Coder generated IP core, see Generate Device Tree for IP Core.

Note

• FPGA data capture over a JTAG connection is available for Intel and Xilinx boards. FPGA data capture over a PL Ethernet, PS Ethernet, or USB Ethernet connection is available for Xilinx boards only.

• To enable the PL Ethernet connection, you must add the Ethernet MAC Hub IP in the plugin_board file by using the addEthernetMACInterface method. Adding the PL Ethernet connection in the plugin_rd file, without adding the Ethernet MAC Hub IP in the plugin_board file, results in an error.

Example: {'JTAG'}

Example: {'JTAG','PS Ethernet'}

Example: {'JTAG','PS Ethernet','USB Ethernet'}

Manager_Connection — Manager port name

character vector

Name of the AXI4 manager port of the processor that is connected to the AXI4 subordinate port of the FPGA Data Capture interface, specified as a character vector.

Example: 'axi_cpu_interconnect/M01_AXI'

Manager_Address_Segments — Manager address segments

cell array of character vectors

Target address segments of the AXI4 manager port of the processor, specified as a cell array of character vectors. The format of the target address segments is {'SegmentName',offset address,range}. You must use a power of 2 value for range.

Note

The interface supports the address width of 32 bits and the register address space of 28 bits.

Example: {'sys_cpu/Data',hex2dec('0x50000000'),hex2dec('0x00100000')}

Manager_Clock_Connection — Manager clock port name

character vector

Name of the AXI4 manager clock port of the processor that is connected to the AXI4 subordinate clock port of the FPGA Data Capture interface, specified as a character vector.

Example: 'core_clkwiz/clk_out1'

Manager_Reset_Connection — Manager reset port name

character vector

Name of the AXI4 manager reset port of the processor that is connected to the AXI4 subordinate reset port of the FPGA Data Capture interface, specified as a character vector.

Example: 'proc_sys_reset_user/peripheral_aresetn'

Memory_Connection — Memory port name

character vector

Name of the AXI4 subordinate port of the memory that is connected to the AXI4 manager port of the FPGA Data Capture interface, specified as a character vector.

Example: 'axi_plddr_interconnect/S02_AXI'

Memory_Address_Segments — Memory address segments

cell array of character vectors

Target address segments of the AXI4 subordinate port of the memory, specified as a cell array of character vectors. The format of the target address segments is {'SegmentName',offset address,range}. You must use a power of 2 value for range.

Example: {'mig_7series_0/memmap/memaddr',0x40000000,PLDDRSize}

Memory_Clock_Connection — Memory clock port name

character vectors

Name of the clock port of the memory that is connected to the AXI4 manager clock port of the FPGA Data Capture interface, specified as a character vector.

Example: 'mig_7series_0/ui_clk'

Memory_Reset_Connection — Memory reset port name

character vectors

Name of the reset port of the memory that is connected to the AXI4 manager reset port of the FPGA Data Capture interface, specified as a character vector.

Example: 'proc_sys_reset_1/peripheral_aresetn'

Examples

Add FPGA Data Capture Interface to Reference Design Object

Add an FPGA Data Capture interface to an hdlcoder.ReferenceDesign object, with the manager port connecting to external DDR memory and the subordinate port connecting to the processor.

Create a reference design object.

hRD = hdlcoder.ReferenceDesign('SynthesisTool','Xilinx Vivado');
hRD.ReferenceDesignName = 'Data Capture IP with External DDR3 Memory Access';
hRD.BoardName = 'Xilinx Zynq ZC706 evaluation kit';

Add the supported tool versions.

hRD.SupportedToolVersion = {'2023.1','2024.1'};

Add an FPGA Data Capture interface with AXI4 manager and AXI4 subordinate ports.

PLDDRSize = 1024*2^20;
hRD.addFPGADataCaptureInterface(...
    'AllowedConnectivityTypes',{'JTAG','PS Ethernet','USB Ethernet'}, ...
    'ManagerConnection','axi_cpu_interconnect/M01_AXI', ...
    'ManagerAddressSegments',{'sys_cpu/Data',hex2dec('0x50000000'),hex2dec('0x00100000')}, ...
    'ManagerClockConnection','core_clkwiz/clk_out1', ...
    'ManagerResetConnection','proc_sys_reset_user/peripheral_aresetn', ...
    'MemoryConnection','axi_plddr_interconnect/S02_AXI', ... 
    'MemoryAddressSegments',{'mig_7series_0/memmap/memaddr',0x40000000,PLDDRSize}, ...
    'MemoryClockConnection','mig_7series_0/ui_clk', ...
    'MemoryResetConnection', proc_sys_reset_1/peripheral_aresetn');

Version History

Introduced in R2025a