addFPGADataCaptureInterface
Class: hdlcoder.ReferenceDesign
Namespace: hdlcoder
Syntax
addFPGADataCaptureInterface('AllowedConnectivityTypes',{'JTAG'})
addFPGADataCaptureInterface('AllowedConnectivityTypes',Connection_Types,'ManagerConnection',Manager_Connection,'ManagerAddressSegments',Manager_Address_Segments,'ManagerClockConnection',Manager_Clock_Connection,'ManagerResetConnection',Manager_Reset_Connection)
addFPGADataCaptureInterface('AllowedConnectivityTypes',{'JTAG'},'MemoryConnection',Memory_Connection,'MemoryAddressSegments',Memory_Address_Segments,'MemoryClockConnection',Memory_Clock_Connection,'MemoryResetConnection',Memory_Reset_Connection)
addFPGADataCaptureInterface('AllowedConnectivityTypes',Connection_Types,'ManagerConnection',Manager_Connection,'ManagerAddressSegments',Manager_Address_Segments,'ManagerClockConnection',Manager_Clock_Connection,'ManagerResetConnection',Manager_Reset_Connection,'MemoryConnection',Memory_Connection,'MemoryAddressSegments',Memory_Address_Segments,'MemoryClockConnection',Memory_Clock_Connection,'MemoryResetConnection',Memory_Reset_Connection)
Description
addFPGADataCaptureInterface('AllowedConnectivityTypes',
adds and defines an FPGA Data Capture interface to an {'JTAG'}
)hdlcoder.ReferenceDesign
object. This argument enables data capture over a JTAG connection and uses internal BRAM
resources to store captured data.
addFPGADataCaptureInterface('AllowedConnectivityTypes',
adds and defines an FPGA Data Capture interface to the Connection_Types
,'ManagerConnection',Manager_Connection
,'ManagerAddressSegments',Manager_Address_Segments
,'ManagerClockConnection',Manager_Clock_Connection
,'ManagerResetConnection',Manager_Reset_Connection
)hdlcoder.ReferenceDesign
object with the options to connect to the AXI4 manager port of the processor. These arguments
enable data capture over a processing system (PS) Ethernet or universal serial bus (USB)
Ethernet connection and use internal BRAM resources to store captured data. In the HDL
Workflow Advisor, HDL Coder™ adds connections specified by the Connection_Types
argument
to the FPGA Data Capture (HDL Verifier required) parameter in the
Set Target Reference Design task.
addFPGADataCaptureInterface('AllowedConnectivityTypes',
adds and defines an FPGA Data Capture interface to the {'JTAG'}
,'MemoryConnection',Memory_Connection
,'MemoryAddressSegments',Memory_Address_Segments
,'MemoryClockConnection',Memory_Clock_Connection
,'MemoryResetConnection',Memory_Reset_Connection
)hdlcoder.ReferenceDesign
object with the options to connect to external DDR memory. These arguments enable capturing
large data of up to two gigasamples by using the external DDR memory available on the FPGA
board over a JTAG connection. When you specify these arguments, in the HDL Workflow Advisor,
HDL Coder adds the External memory
option to the FPGA
Data Capture storage type parameter in the Generate RTL Code and IP
Core task.
addFPGADataCaptureInterface('AllowedConnectivityTypes',
adds and defines an FPGA Data Capture interface to the Connection_Types
,'ManagerConnection',Manager_Connection
,'ManagerAddressSegments',Manager_Address_Segments
,'ManagerClockConnection',Manager_Clock_Connection
,'ManagerResetConnection',Manager_Reset_Connection
,'MemoryConnection',Memory_Connection
,'MemoryAddressSegments',Memory_Address_Segments
,'MemoryClockConnection',Memory_Clock_Connection
,'MemoryResetConnection',Memory_Reset_Connection
)hdlcoder.ReferenceDesign
object with the options to connect to the AXI4 manager port of the processor and external DDR
memory. These arguments enable capturing large data of up to two gigasamples by using the
external DDR memory over a PS Ethernet or USB Ethernet connection.
Key Considerations
This interface is supported only for the Intel® and Xilinx® synthesis tools.
If you do not define this interface in the
plugin_rd
reference design definition file, the following syntax is applied by default:addFPGADataCaptureInterface('AllowedConnectivityTypes',{'JTAG'})
Input Arguments
Examples
Version History
Introduced in R2025a